4 Commits

Include renames

Author	SHA1	Message	Date
Blaise Tine	e64996946d	using 44-bit perf counters - aligned with DSP counters width	2021-02-28 02:05:47 -08:00
Blaise Tine	d956e268b9	adding new performance counters (banks utilization and DRAM bus utilization)	2020-12-22 12:33:45 -08:00
Blaise Tine	d5438fd591	merging perf counters	2020-12-08 21:02:39 -08:00
Xandy Liu	1595ff08e2	PERF pipeline stalls and cache	2020-12-08 01:14:41 -05:00