13 Commits

Include renames

Author	SHA1	Message	Date
Blaise Tine	d91d56d126	block ram refactoring (multi-porting supporting and simulation support)	2021-08-26 08:19:44 -07:00
Blaise Tine	7961cf7474	Disabling tracing on library	2021-08-12 01:55:52 -07:00
Blaise Tine	ea1e0f201e	OUTPUT_REG refactoring	2021-07-23 06:58:37 -07:00
Blaise Tine	5c58f7eec6	minor update	2021-07-16 12:57:50 -07:00
Blaise Tine	c5aec572b5	minor update	2021-07-15 11:46:43 -07:00
Blaise Tine	ed216ab39d	minor updates	2021-01-17 13:58:43 -08:00
Blaise Tine	d44144f72f	FPU float<->int conversion optimization	2020-12-29 15:37:45 -08:00
Blaise Tine	d0f2a3984d	adding input buffering to bus arbiters to reduce backpressure delay propagation	2020-12-05 17:31:29 -08:00
Blaise Tine	b677f724aa	Use skid buffer on CSR IO bus to stop backpressure delay propagation into csr_unit	2020-12-01 12:37:15 -08:00
Blaise Tine	af84e01856	minor update	2020-08-31 06:17:49 -07:00
Blaise Tine	0b355f228e	ibuffer addition	2020-08-22 00:22:04 -07:00
Blaise Tine	6c12391338	pipeline refactoring - fmax >= 222 mhz	2020-08-14 21:50:14 -07:00
Blaise Tine	65415d2bbc	getting dogfood tests passing on Verilator!	2020-08-09 18:13:12 -04:00