6 Commits

Author	SHA1	Message	Date
felsabbagh3	84f5ccb484	Added CSR TID/WID reads	2019-10-21 02:10:05 -04:00
felsabbagh3	ee83e6d8c8	Moved GPR to back-end	2019-10-14 19:08:32 -04:00
felsabbagh3	719ed25213	Cleanup	2019-03-31 16:30:37 -04:00
felsabbagh3	a3a3b21de7	Using verilog For-loops + Passing all tests	2019-03-30 22:09:03 -04:00
felsabbagh3	99a0792a0c	Passing all tests with 2 threads	2019-03-30 03:54:20 -04:00
felsabbagh3	7a528c5ef2	Packing data wires + ALU module	2019-03-26 19:17:11 -04:00