Commit Graph

23 Commits

Author SHA1 Message Date
Blaise Tine
f68af3bb84 using mshr pending request size 2020-12-01 00:54:25 -08:00
Blaise Tine
def6a35693 shared memory optimization 2020-11-29 15:04:31 -08:00
Blaise Tine
b85391389b rename MSRQ to MSHR 2020-11-28 17:32:00 -05:00
Blaise Tine
1795980a52 L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization 2020-11-21 09:47:56 -08:00
Blaise Tine
5d58bf3d11 fixed l3cache hang using memory arbiter in afu 2020-11-15 06:36:32 -08:00
Blaise Tine
c39f98a8af merge 2020-11-10 16:48:36 -05:00
Blaise Tine
725322807e fixed DRAM response backpressure inside Cache 2020-11-10 05:24:57 -08:00
Blaise Tine
323d2a3b3e minor fix 2020-11-03 15:34:35 -08:00
Blaise Tine
ba81d76e02 cache refactoring - phase 2 2020-11-03 04:51:40 -08:00
Blaise Tine
5be1d85648 cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count 2020-11-02 01:50:12 -08:00
Blaise Tine
4bfc4ee78f scope fixes 2020-10-13 08:44:55 -07:00
Blaise Tine
32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
Blaise Tine
4e1007e5b2 scope refactoring 2020-10-03 18:53:21 -04:00
Blaise Tine
f6f95e0c46 mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL 2020-09-19 14:45:42 -04:00
Blaise Tine
49b86c4b2a SCOPE update 2020-09-05 10:52:59 -07:00
Blaise Tine
c63217f67d fixed SCOPE interface 2020-09-01 05:20:13 -07:00
Blaise Tine
31ffbe0d6a clean up 'stage_1_cycles' from cache 2020-09-01 03:39:03 -07:00
Blaise Tine
6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
Blaise Tine
83a1695c73 OPAE CSR access 2020-06-30 18:14:06 -07:00
Blaise Tine
582a00d690 adding OPAE CSR support 2020-06-30 10:05:57 -07:00
felsabbagh3
b8e8cab1ee Added CSR IO req/rsp V0.1 2020-06-29 23:00:34 -07:00
Blaise Tine
8302641510 fpga fixes 2020-06-27 14:03:20 -07:00
Blaise Tine
5e718c2676 refactoring 2020-06-23 09:54:40 -07:00