Blaise Tine
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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Blaise Tine
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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7560202f8b
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cache bank refactoring - removing unecessary core response fifo & restoring single port data access
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2021-02-21 21:47:46 -08:00 |
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Blaise Tine
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ccb74ef286
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cache data access with decoupled read/write ports
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2021-02-21 15:18:24 -08:00 |
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Blaise Tine
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05f93fac20
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minor update
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2021-02-20 13:15:15 -08:00 |
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Blaise Tine
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9eed48435c
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instruction decode optimization
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2021-02-14 00:19:54 -08:00 |
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Blaise Tine
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3c37db877a
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cache specialization for in-order DRAM reponses
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2021-02-13 20:23:29 -08:00 |
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Blaise Tine
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665b97b810
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multi-ported cache support for streaming
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2021-02-08 16:13:32 -08:00 |
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Blaise Tine
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111cc29482
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minor update
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2021-02-04 15:28:04 -08:00 |
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Blaise Tine
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32b94f61f2
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minor update
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2021-02-01 11:00:09 -08:00 |
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Blaise Tine
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62ff97d6e1
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minor update - smem perf update
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2021-02-01 10:29:20 -08:00 |
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Blaise Tine
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dc18bfabb8
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minor update - remove mshr data store
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2021-01-30 06:40:48 -08:00 |
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Blaise Tine
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5419859281
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fcvt fix
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2021-01-25 02:22:00 -08:00 |
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Blaise Tine
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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Blaise Tine
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74a687e395
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minor updates
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2021-01-18 05:43:30 -08:00 |
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Blaise Tine
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a7f6b9fffc
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minor updates
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2021-01-17 18:18:05 -08:00 |
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Blaise Tine
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8b42393189
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minor updates
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2021-01-17 17:33:41 -08:00 |
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Blaise Tine
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a046bd7a73
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cache pipeline optimization
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2021-01-17 17:19:52 -08:00 |
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Blaise Tine
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ed216ab39d
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minor updates
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2021-01-17 13:58:43 -08:00 |
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Blaise Tine
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a69ba5ad7b
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cache flush support
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2021-01-17 05:50:29 -08:00 |
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Blaise Tine
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d4e7b28be8
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cache refactoring
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2021-01-17 00:18:56 -08:00 |
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Blaise Tine
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4f26228d50
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minor updates
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2021-01-16 05:33:28 -08:00 |
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Blaise Tine
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fcbf57b66a
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specialized shared memory module
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2021-01-16 04:41:58 -08:00 |
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Blaise Tine
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f146178c2d
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minor updates
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2021-01-13 15:52:03 -08:00 |
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Blaise Tine
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0e1650e1c2
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bank deadlock fix
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2021-01-13 15:51:42 -08:00 |
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Blaise Tine
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79cc4d98e6
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bank deadlock fix
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2021-01-13 13:06:07 -08:00 |
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Blaise Tine
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464c4f4bd8
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minor updates
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2021-01-12 20:16:59 -08:00 |
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Blaise Tine
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e770824d47
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fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
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2021-01-10 20:26:15 -08:00 |
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Blaise Tine
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06945533cf
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fixed l2/l3 caches related bugs
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2021-01-09 16:32:55 -08:00 |
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Blaise Tine
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2058718f0f
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minor updates
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2021-01-06 07:18:14 -08:00 |
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Blaise Tine
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31ff70fd4e
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minor updates
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2021-01-05 15:03:41 -08:00 |
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Blaise Tine
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846a4036d3
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minor update
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2021-01-05 05:46:20 -08:00 |
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Blaise Tine
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39bff921be
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cache bug fixes
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2021-01-05 05:04:49 -08:00 |
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Blaise Tine
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762b8e2e3e
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fixed cache mshr critical path
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2021-01-04 12:49:40 -05:00 |
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Blaise Tine
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4d55118545
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cache pipeline optimization - moved tag access to stage0
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2021-01-03 23:10:41 -05:00 |
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Blaise Tine
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9cef1aae04
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cache fill response address is the mshr's top address, no need to store it
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2021-01-03 00:57:24 -05:00 |
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Blaise Tine
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a825941f51
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-01-02 16:06:09 -05:00 |
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Blaise Tine
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2d69ca5d67
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scratchpad optimization for stack access using custom bank offset aligned to stack size
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2021-01-02 16:00:00 -05:00 |
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Blaise Tine
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93c36273fa
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minor update
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2021-01-01 20:24:18 -08:00 |
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Blaise Tine
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b2cfde5d6d
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enabling shared memory back
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2020-12-31 19:19:14 -08:00 |
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Blaise Tine
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abe32ed553
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cache optimization - moved read requests to stage1 and eliminating stage3
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2020-12-31 07:40:58 -08:00 |
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Blaise Tine
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d44144f72f
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FPU float<->int conversion optimization
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2020-12-29 15:37:45 -08:00 |
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Blaise Tine
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703a861fe9
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added support for write-through cache, removed cache snooping support
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2020-12-23 23:51:02 -08:00 |
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Blaise Tine
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d956e268b9
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adding new performance counters (banks utilization and DRAM bus utilization)
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2020-12-22 12:33:45 -08:00 |
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Blaise Tine
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4b7d871d62
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allowing partial cache request submissions, io bus support broken
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2020-12-21 03:53:13 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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d5438fd591
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merging perf counters
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2020-12-08 21:02:39 -08:00 |
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Blaise Tine
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d5fa82f5e4
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cache req datapath optimizations
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2020-12-08 02:58:08 -08:00 |
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Xandy Liu
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1595ff08e2
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PERF pipeline stalls and cache
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2020-12-08 01:14:41 -05:00 |
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