wu-arch/kernels
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688c9892d5f27bf6e53d194246a3ee34eb952f37
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4 Commits

Author SHA1 Message Date
Blaise Tine
cd29362d10 fixed FPU handshake, optimized writeback's critical path 2020-08-07 10:11:54 -07:00
Blaise Tine
ffd9515881 added altera fpu modules 2020-08-05 15:53:59 -07:00
Blaise Tine
a70562d386 set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18 2020-06-29 08:03:19 -07:00
Blaise Tine
68d9fc9a75 driver basic test and demo test refactoring 2020-06-19 09:12:07 -07:00