12 Commits

Include renames

Author	SHA1	Message	Date
Blaise Tine	8775f63ec4	lkg build rollout with 16cores optimization on arria10	2021-01-24 16:49:22 -08:00
Blaise Tine	d0f2a3984d	adding input buffering to bus arbiters to reduce backpressure delay propagation	2020-12-05 17:31:29 -08:00
Blaise Tine	f3b1069ce8	adding stream arbiter	2020-12-03 06:40:23 -08:00
Blaise Tine	97739e9dcf	RAM blocks inference fixes	2020-11-30 14:02:47 -08:00
Blaise Tine	6c12391338	pipeline refactoring - fmax >= 222 mhz	2020-08-14 21:50:14 -07:00
Blaise Tine	c2dd0a8b39	modelsim fixes && pipeline optimization	2020-07-28 14:20:23 -07:00
Blaise Tine	25f66e6490	pipeline refactoring	2020-07-19 05:03:47 -04:00
Blaise Tine	bdfacf709c	yosys synthesis refactoring	2020-07-10 18:56:41 -04:00
Blaise Tine	8302641510	fpga fixes	2020-06-27 14:03:20 -07:00
Blaise Tine	d3440de403	round robin arbiter + auto buffered queue + fixed dcache arbiter	2020-06-20 17:56:04 -04:00
Blaise Tine	d6c87dbb0a	added debug print states or rtl	2020-05-16 14:19:17 -04:00
Blaise Tine	d623ef4029	snooping response handling fix	2020-05-14 23:05:46 -04:00