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c1e168fdbe
Vortex 2.0 changes:
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+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
minor update
minor update
minor update
minor update
minor update
cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor updates
minor updates
minor update
minor update
2023-11-10 02:47:05 -08:00
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d48f1c1c5f
minor updates
2022-02-01 06:53:31 -05:00
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41d7e6c63a
cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
2021-11-30 07:08:15 -05:00
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bf72800676
debug tracing refactoring
2021-10-17 13:42:16 -07:00
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8e82ee00a0
minor update
2021-09-29 09:32:21 -07:00
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04249c3ee9
code refactoring for Vivado compatibility
2021-09-29 04:48:53 -04:00
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a45261b530
code refactoring for Vivado compatibility
2021-09-29 03:24:17 -04:00
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132260d84c
minor update
2021-09-27 09:23:58 -04:00
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9f34b2944c
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
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9b04f3d9d6
Updated README and synthesis scripts
2021-09-22 07:50:47 -07:00
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feca2db24e
critical path optimizations
2021-09-15 04:50:45 -07:00
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83d80c061f
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-09-14 05:11:28 -04:00
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3d7baf1640
block ram read enable fix
2021-09-14 01:45:01 -07:00
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6652e2f0e9
minor update
2021-09-11 18:16:08 -07:00
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6f09fb8ba5
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-09-11 18:26:08 -04:00
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95287980af
minor update
2021-09-11 15:14:17 -07:00
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0dfdf6cd4d
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-09-10 06:03:32 -04:00
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5192846c72
minor updates
2021-09-10 02:57:05 -07:00
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18172fa611
AXI memory bus support
2021-09-10 01:36:01 -07:00
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ca46b0a0be
OUTPUT_REG => OUT_REG renaming
2021-09-09 03:05:38 -07:00
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a46c32ed4b
Adding Vortex Yosys build support
2021-09-08 23:04:33 -04:00
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c06efbf480
minor update
2021-09-07 23:47:41 -07:00
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0d91f8771e
Workaround fix for Verilator bug with array indexing
2021-09-07 23:28:54 -07:00
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d42baf34ff
minor update
2021-09-06 23:44:31 -07:00
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af1cecae07
stream arbiter update
2021-09-06 23:38:20 -07:00
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b52ace5142
area optimization bundle
2021-09-05 23:35:44 -07:00
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fe5112b6c1
minor updates
2021-09-05 23:05:21 -07:00
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377466ed1c
fpu area optimization
2021-09-05 21:01:52 -07:00
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f3ba27b138
GPRs optimization - disabling BRAM's read-during-write bypass block.
2021-08-28 15:34:36 -07:00
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28eb3cfdb2
minor update
2021-08-26 14:49:57 -07:00
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74a45e2772
stream arbiter optimization (using indexing instead of onehot mux)
2021-08-26 09:52:13 -07:00
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d91d56d126
block ram refactoring (multi-porting supporting and simulation support)
2021-08-26 08:19:44 -07:00
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e494860f38
using lzc instead of priority_encoder
2021-08-26 07:29:47 -07:00
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2a27bfbfd5
LKG Build (reset network update -fmax=236 mhz 4c)
2021-08-23 01:59:22 -07:00
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eef3dda81d
fixed Verilator error
2021-08-13 19:33:12 -07:00
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646371f9e9
bram block optimization
2021-08-13 19:31:55 -07:00
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f12be56d7c
fixed Verilator warnings
2021-08-13 05:52:43 -04:00
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7961cf7474
Disabling tracing on library
2021-08-12 01:55:52 -07:00
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7b8fe11e6a
unused variables refactoring
2021-08-05 01:46:26 -07:00
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79fd92a1b4
minor update
2021-07-30 17:43:15 -07:00
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160ff94a22
minor update
2021-07-30 16:01:22 -07:00
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3d19588e57
bus arbiters refactoring
2021-07-30 16:00:09 -07:00
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ea1e0f201e
OUTPUT_REG refactoring
2021-07-23 06:58:37 -07:00
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5c58f7eec6
minor update
2021-07-16 12:57:50 -07:00
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a8f9a2559d
minor update
2021-07-15 12:25:51 -07:00
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c5aec572b5
minor update
2021-07-15 11:46:43 -07:00
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7d01be367c
reset network refactoring
2021-07-15 11:34:55 -07:00
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22cf698e69
minor update
2021-07-13 05:25:44 -07:00
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10e9ee124b
using onehot multiplexer to reduce critical path
2021-07-08 00:26:59 -07:00
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dc34c5c5bd
minor update
2021-07-03 04:47:19 -07:00
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