Commit Graph

150 Commits

Author SHA1 Message Date
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ba1082249a minor update 2021-01-06 23:30:30 -08:00
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82fa3b850e minor update 2021-01-06 22:31:25 -08:00
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146c285aa0 minor update 2021-01-06 19:59:04 -08:00
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2058718f0f minor updates 2021-01-06 07:18:14 -08:00
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31ff70fd4e minor updates 2021-01-05 15:03:41 -08:00
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d44144f72f FPU float<->int conversion optimization 2020-12-29 15:37:45 -08:00
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703a861fe9 added support for write-through cache, removed cache snooping support 2020-12-23 23:51:02 -08:00
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4bbd7bf408 performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies, 2020-12-19 02:45:06 -08:00
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29cd2f5dff fixed register file initialization to zero synthesis inference 2020-12-10 00:27:56 -08:00
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d5438fd591 merging perf counters 2020-12-08 21:02:39 -08:00
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14baec86d5 moved apae sources into rtl/afu 2020-12-08 04:59:11 -08:00
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d5fa82f5e4 cache req datapath optimizations 2020-12-08 02:58:08 -08:00
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5074038ad6 minor update 2020-12-06 22:41:14 -08:00
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d68b32cd60 minor update 2020-12-06 22:40:27 -08:00
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1332970636 refactoring cores clustering 2020-12-06 14:42:12 -08:00
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f3b1069ce8 adding stream arbiter 2020-12-03 06:40:23 -08:00
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84a9f1e2d7 minor update 2020-12-01 12:00:05 -08:00
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f9d98c5a2b fixed bank_core_req_arb critical path. 2020-12-01 08:47:52 -08:00
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def6a35693 shared memory optimization 2020-11-29 15:04:31 -08:00
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ac1883a13f tabs cleanup 2020-11-28 17:08:01 -05:00
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20f22c7446 scope minor fix 2020-11-22 11:51:46 -08:00
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1795980a52 L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization 2020-11-21 09:47:56 -08:00
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a1fcdd467a reset networks optimization 2020-11-16 01:12:02 -08:00
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5d58bf3d11 fixed l3cache hang using memory arbiter in afu 2020-11-15 06:36:32 -08:00
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fceb561cbd synchronous reset network optimization: only reset register when required 2020-11-11 20:54:54 -08:00
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7c384eaf7f fixed snoop forwarding hang 2020-11-09 20:02:33 -08:00
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f8d54c6994 fixed cache_core_rsp_merge unit 2020-11-09 02:10:35 -08:00
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203a184008 fixed bank_core_req_abr critical path 2020-11-08 18:25:32 -08:00
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10505caae1 refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2 2020-11-08 01:31:46 -08:00
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ba81d76e02 cache refactoring - phase 2 2020-11-03 04:51:40 -08:00
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5be1d85648 cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count 2020-11-02 01:50:12 -08:00
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3fe31fc337 fixed afu to cpu mempcy hang 2020-10-28 14:19:13 -07:00
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9a9f7955f0 basic test timing + scope tracing ccip 2020-10-27 17:04:04 -04:00
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48897d9778 minor update 2020-10-25 18:29:25 -07:00
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43ae82e788 vlsim fix, verilator fst trace, use ram optimization 2020-10-25 16:40:50 -07:00
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e6466b887c minor update 2020-10-20 08:45:21 -07:00
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7529f72c5d fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags 2020-10-20 05:32:55 -07:00
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301cc45740 scope fixes 2020-10-14 09:19:26 -07:00
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58b8e82908 scope fixes ... 2020-10-13 17:09:22 -04:00
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4bfc4ee78f scope fixes 2020-10-13 08:44:55 -07:00
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32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
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309dd48fc6 scope bug fixes 2020-10-06 03:59:27 -04:00
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4e1007e5b2 scope refactoring 2020-10-03 18:53:21 -04:00
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91f348c61a adding prebuilt CI script 2020-09-19 16:08:28 -04:00
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f6f95e0c46 mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL 2020-09-19 14:45:42 -04:00
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80f929eb61 fixed build warnings; sgemm Makefile 2020-09-10 13:39:34 -04:00
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fba2fa03c7 fixed new AFU Driver bugs - now functional 2020-09-09 17:05:48 -04:00
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bf7b0cf340 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2020-09-08 13:05:47 -04:00
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0fab1ddd92 adding support for verilator-driven AFU driver: vlsim 2020-09-08 13:05:26 -04:00
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36ec603d17 fpga fixes: warp scheduler, fnmadd, fdiv, fsqrt 2020-09-08 07:05:26 -07:00