felsabbagh3
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b216da5a6a
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ram stdint + Quartus Files
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2019-06-11 21:13:30 -07:00 |
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felsabbagh3
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d7afef04a9
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Sim Work miss
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2019-05-18 23:42:55 +04:00 |
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felsabbagh3
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a6c13bc38c
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Inefficient context aware desgin
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2019-05-08 15:55:06 -07:00 |
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felsabbagh3
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79356c7ab1
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Changed hierarchy + Identified private + public modules
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2019-05-07 23:45:05 -07:00 |
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felsabbagh3
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f21eaec79f
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Provisioned SM
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2019-04-05 19:25:54 -04:00 |
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felsabbagh3
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8c2ae97510
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1 WARP 8 THREADS TESTED + FULLY WORKING
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2019-03-31 05:21:00 -04:00 |
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felsabbagh3
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c83ef94d02
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1 WARP 2 THREADS WORKING
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2019-03-31 05:02:55 -04:00 |
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felsabbagh3
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52a839f84d
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Using verilog For-loops + Passing all tests
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2019-03-30 22:14:44 -04:00 |
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felsabbagh3
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99a0792a0c
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Passing all tests with 2 threads
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2019-03-30 03:54:20 -04:00 |
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felsabbagh3
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d02c3d25b7
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sync
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2019-03-27 13:52:13 -04:00 |
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felsabbagh3
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9b42e79dcf
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Added HW threads - Infinite loop
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2019-03-27 03:44:14 -04:00 |
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felsabbagh3
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097e0217de
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Added support for MUL/DIV (Passes all tests)
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2019-03-22 03:54:59 -04:00 |
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felsabbagh3
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656475b3b3
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Passing Most tests
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2019-03-21 23:47:48 -04:00 |
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