16 Commits

Include renames

Author	SHA1	Message	Date
Blaise Tine	5be1d85648	cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count	2020-11-02 01:50:12 -08:00
Blaise Tine	9a9f7955f0	basic test timing + scope tracing ccip	2020-10-27 17:04:04 -04:00
Blaise Tine	58b8e82908	scope fixes ...	2020-10-13 17:09:22 -04:00
Blaise Tine	4bfc4ee78f	scope fixes	2020-10-13 08:44:55 -07:00
Blaise Tine	32da50816f	scope refactoring: adding modules definitions to VCD trace	2020-10-12 23:26:02 -04:00
Blaise Tine	309dd48fc6	scope bug fixes	2020-10-06 03:59:27 -04:00
Blaise Tine	4e1007e5b2	scope refactoring	2020-10-03 18:53:21 -04:00
Blaise Tine	49b86c4b2a	SCOPE update	2020-09-05 10:52:59 -07:00
Blaise Tine	c63217f67d	fixed SCOPE interface	2020-09-01 05:20:13 -07:00
Blaise Tine	6c12391338	pipeline refactoring - fmax >= 222 mhz	2020-08-14 21:50:14 -07:00
Blaise Tine	1f63f9da25	new fpu implementation	2020-07-24 00:00:37 -04:00
Blaise Tine	25f66e6490	pipeline refactoring	2020-07-19 05:03:47 -04:00
Blaise Tine	baf7d3bb92	minor update	2020-06-27 17:46:45 -04:00
Blaise Tine	8302641510	fpga fixes	2020-06-27 14:03:20 -07:00
Blaise Tine	0a01385a2c	few updates	2020-06-23 09:28:24 -07:00
Blaise Tine	68d9fc9a75	driver basic test and demo test refactoring	2020-06-19 09:12:07 -07:00