Commit Graph

22 Commits

Author SHA1 Message Date
Blaise Tine
4e1007e5b2 scope refactoring 2020-10-03 18:53:21 -04:00
Blaise Tine
42e3b6c45d fixed lmp_mult parameters, ram init filepath 2020-09-04 07:51:46 -07:00
Blaise Tine
c2dd0a8b39 modelsim fixes && pipeline optimization 2020-07-28 14:20:23 -07:00
Blaise Tine
d3440de403 round robin arbiter + auto buffered queue + fixed dcache arbiter 2020-06-20 17:56:04 -04:00
Blaise Tine
68d9fc9a75 driver basic test and demo test refactoring 2020-06-19 09:12:07 -07:00
Blaise Tine
d6b0ef2b3c scope refactoring + snoop invalidate 2020-06-12 00:04:31 -07:00
Blaise Tine
4e0e710182 OPAE rtl fixes 2020-06-04 15:44:03 -07:00
Blaise Tine
9b186dcc6e fixed L2 cache 2020-06-02 05:32:50 -07:00
Blaise Tine
16d5a8a09c opae rtl fixes 2020-05-31 14:51:42 -07:00
Blaise Tine
9e5885b820 adding dram writeenable support + scheduler bug fixes 2020-05-27 19:00:23 -04:00
Blaise Tine
3a9e79d979 revert byte_enable tag structure 2020-05-23 22:23:25 -04:00
Blaise Tine
d6c87dbb0a added debug print states or rtl 2020-05-16 14:19:17 -04:00
Blaise Tine
bcb9514799 snooping response handling fix 2020-05-14 11:01:41 -04:00
felsabbagh3
b08b80156d Added pending request check. This applies when 1) mrvq entery is valid/ready but not head, then a core request hits 2) snoop when pending write. A pending miss request is either a valid entry in mrvq OR a miss entery in st2 2020-05-12 21:25:13 -07:00
Blaise Tine
de9fc68ccc opae fixes 2020-05-06 21:14:53 -07:00
Blaise Tine
330bbc4f56 rtl gpr multicore fix 2020-05-06 09:05:10 -04:00
Blaise Tine
f142afac80 rtl refactoring 2020-05-04 20:12:05 -04:00
Blaise Tine
a1dc90b951 rtl cache refactory 2020-04-30 17:12:18 -04:00
Blaise Tine
20ae78f434 fix simX build 2020-04-21 01:31:32 -04:00
Blaise Tine
d79e36912f fix opae build 2020-04-20 12:51:42 -07:00
Blaise Tine
b76f8696bd removing *.vh file for opae build 2020-04-20 15:07:27 -04:00
Blaise Tine
e8a4923eb4 RTL code refactoring 2020-04-20 12:09:30 -04:00