Blaise Tine
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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Blaise Tine
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d4e7b28be8
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cache refactoring
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2021-01-17 00:18:56 -08:00 |
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Blaise Tine
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e770824d47
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fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
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2021-01-10 20:26:15 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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13a5370254
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register file refactoring
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2020-12-05 01:40:50 -08:00 |
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Blaise Tine
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97739e9dcf
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RAM blocks inference fixes
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2020-11-30 14:02:47 -08:00 |
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Blaise Tine
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ac1883a13f
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tabs cleanup
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2020-11-28 17:08:01 -05:00 |
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Blaise Tine
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eb307edd9c
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minor update
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2020-11-23 17:34:06 -08:00 |
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Blaise Tine
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725322807e
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fixed DRAM response backpressure inside Cache
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2020-11-10 05:24:57 -08:00 |
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Blaise Tine
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af2bb3b789
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cache fixes and opyimization - fmax moved from 162 mhz to 220 mhz!!!
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2020-11-05 03:49:50 -08:00 |
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Blaise Tine
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4c6a74fa87
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cache refactoring - phase 3 - added dedicated pipeline stage for tag access
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2020-11-04 03:21:30 -08:00 |
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Blaise Tine
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ba81d76e02
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cache refactoring - phase 2
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2020-11-03 04:51:40 -08:00 |
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Blaise Tine
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43ae82e788
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vlsim fix, verilator fst trace, use ram optimization
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2020-10-25 16:40:50 -07:00 |
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Blaise Tine
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7529f72c5d
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fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags
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2020-10-20 05:32:55 -07:00 |
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