Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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14baec86d5
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moved apae sources into rtl/afu
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2020-12-08 04:59:11 -08:00 |
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Blaise Tine
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84a9f1e2d7
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minor update
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2020-12-01 12:00:05 -08:00 |
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Blaise Tine
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f9d98c5a2b
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fixed bank_core_req_arb critical path.
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2020-12-01 08:47:52 -08:00 |
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Blaise Tine
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10505caae1
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refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2
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2020-11-08 01:31:46 -08:00 |
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Blaise Tine
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0a45a8beb3
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minor update
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2020-09-01 00:56:10 -07:00 |
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Blaise Tine
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ff7f65bd1f
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opae build fixes
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2020-07-21 05:44:13 -07:00 |
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Blaise Tine
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a70562d386
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set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18
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2020-06-29 08:03:19 -07:00 |
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