wu-arch/kernels
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779 Commits 9 Branches 0 Tags
299e3aa72fb879615b9f4e592b68c15319c4bd6d
Commit Graph
364 Commits
Author SHA1 Message Date
felsabbagh3 52a839f84d Using verilog For-loops + Passing all tests 2019-03-30 22:14:44 -04:00
felsabbagh3 a3a3b21de7 Using verilog For-loops + Passing all tests 2019-03-30 22:09:03 -04:00
felsabbagh3 99a0792a0c Passing all tests with 2 threads 2019-03-30 03:54:20 -04:00
felsabbagh3 d02c3d25b7 sync 2019-03-27 13:52:13 -04:00
felsabbagh3 68f3ba84e5 Added HW threads - Infinite loop + fixed valid 2019-03-27 03:53:59 -04:00
felsabbagh3 9b42e79dcf Added HW threads - Infinite loop 2019-03-27 03:44:14 -04:00
felsabbagh3 cc0fb0eece better use of valid signal 2019-03-27 00:07:59 -04:00
felsabbagh3 7a528c5ef2 Packing data wires + ALU module 2019-03-26 19:17:11 -04:00
felsabbagh3 781c11c93f Updated TODO 2019-03-22 04:21:21 -04:00
felsabbagh3 6c64fa35f8 Restructure 2019-03-22 04:14:52 -04:00
felsabbagh3 097e0217de Added support for MUL/DIV (Passes all tests) 2019-03-22 03:54:59 -04:00
felsabbagh3 01d142c6e6 rtl passing all tests 2019-03-22 02:44:53 -04:00
felsabbagh3 656475b3b3 Passing Most tests 2019-03-21 23:47:48 -04:00
felsabbagh3 d08d389177 Started on rtl (Finished till decode) 2019-03-21 02:23:10 -04:00