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807 Commits 7 Branches 0 Tags
256dec4768da48ee1acbe201a6ffcc01d63e6764
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6 Commits

Author SHA1 Message Date
wgulian3
ca61801199 Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance 2020-02-22 20:16:13 -05:00
wgulian3
2c40874cc5 Add multi-cycle compat module and use it in ALU 2020-02-21 22:08:09 -05:00
wgulian3
e76d05f7ce Fix issues quartus synthesis issues 2020-02-18 13:24:18 -05:00
wgulian3
d71f8fcc73 Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu. 2020-02-18 13:02:46 -05:00
wgulian3
0211ca4add Add compat divide module and tb 2020-02-04 10:59:05 -05:00
wgulian3
12a4136464 quartus makefile: Support custom Quartus root location 2020-01-24 18:42:03 -05:00
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