felsabbagh3
65fa9285bf
Fixed Flushing and Prefetching
2020-04-04 17:57:35 -07:00
felsabbagh3
36895d6e7c
Fixed miss_add on for snoop replays
2020-03-29 21:21:53 -07:00
felsabbagh3
efac643c66
Added Proper Handshaking to Everything and Fixed a Couple of Bugs
2020-03-29 02:11:14 -07:00
felsabbagh3
313a8e3b4b
All cache bugs fixed - Handshaking
2020-03-28 21:43:02 -07:00
felsabbagh3
5dc9493c61
ALL tests passing - handshake
2020-03-27 21:34:49 -07:00
felsabbagh3
614797e52f
Migrating fpga_synthesis_temp to main
2020-03-27 13:15:23 -07:00
Blaise Tine
6dc3d0d371
refactor VX_define.v
2020-03-27 13:56:16 -04:00
Blaise Tine
3df21b6e71
fixed regression bug with Vortex.v model hanging issue
2020-03-27 13:19:11 -04:00
Blaise Tine
8763adf7bc
update
2020-03-26 04:19:53 -04:00
wgulian3
3b74f071a7
Generate define overrides based on env vars for C and Verilog.
...
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
2020-03-26 04:08:43 -04:00
Blaise Tine
9621acff5b
fixed Modelsim build errors
2020-03-26 03:54:23 -04:00
Blaise Tine
a7eb9a0c38
code refactoring
2020-03-26 03:20:46 -04:00
Blaise Tine
4626389ee2
code refactoring
2020-03-26 01:41:01 -04:00
felsabbagh3
d146070275
Fix for Single-Threaded
2020-03-22 14:44:46 -07:00
wgulian3
1c82f9a11d
revert saxpy change and fix stage_1_cycles not working
2020-03-20 04:49:02 -04:00
wgulian3
05b7ffff12
Add modified RTL files for parameterized builds with VX_define_synth.v
2020-03-20 04:04:15 -04:00
felsabbagh3
fc94168e32
Removed L3 for synthesis
2020-03-13 15:01:46 -07:00
wgulian3
372a1ad905
minor tweaks to appease quartus
...
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
2020-03-10 12:15:30 -04:00
felsabbagh3
13c6cbfa5d
L3 and CLUSTRING WORKS
2020-03-10 02:41:47 -07:00
felsabbagh3
cf0173ae15
Fixed Stall Pipeline Logic
2020-03-09 22:08:46 -07:00
felsabbagh3
e2ffbcf14b
MULTICORE WITH L2 WORKING
2020-03-09 01:17:11 -07:00
felsabbagh3
b5b04a7070
Added Shared Memory
2020-03-08 15:00:53 -07:00
felsabbagh3
2f94b26af0
Icache working
2020-03-08 13:59:35 -07:00
felsabbagh3
f03f3fe037
Fixed all Cache Warnings
2020-03-07 14:34:05 -08:00
felsabbagh3
9bf0add937
Made the cache module configurable for multi-instantiation
2020-03-07 00:49:40 -08:00
Blaise Tine
66a46f81ce
synthesis fixes
2020-03-05 06:58:51 -05:00
felsabbagh3
b0b9b8238e
Passing some cases
2020-03-04 04:05:54 -08:00
felsabbagh3
3a45375596
Fixed Verilator
2020-02-17 19:36:00 -08:00
fares
9e58bf8fb5
Started synthesis script
2019-11-22 00:32:19 -05:00
fares
8acc32372b
8Warp 32Threads for GTCAD synthesis
2019-11-21 23:51:11 -05:00
fares
c4d315dfed
VCD for power
2019-11-21 23:25:51 -05:00
Lyons, Ethan Tyler
c8abd48458
Synthesis Compatible
2019-11-21 21:42:34 -05:00
Lyons, Ethan Tyler
509850192c
Warps/Threads Parameterization
2019-11-21 01:14:50 -05:00
felsabbagh3
70651f0340
Added a pipeline stage + fixed SM param errors
2019-11-13 12:25:28 -05:00
Lyons, Ethan Tyler
2994e607e3
Shared Memory Implemented
2019-11-13 10:06:13 -05:00
felsabbagh3
ef83285c6c
FileIO Schema started
2019-11-12 00:31:30 -05:00
felsabbagh3
7ed88ce4c1
Fixed AA d_cache sizing errors
2019-11-11 15:20:58 -05:00
felsabbagh3
4b2ea58b79
Syn prep
2019-11-11 14:20:15 -05:00
felsabbagh3
b3c7ac435a
added sm defines
2019-11-10 14:01:54 -05:00
felsabbagh3
fbf708e419
Started simX
2019-11-10 01:21:09 -05:00
felsabbagh3
ea7bd485ca
Icache/Dcache finally done + configurability tested:
2019-11-09 00:03:15 -05:00
felsabbagh3
8b81989bfd
Before way logic change
2019-11-08 18:16:40 -05:00
Lyons, Ethan Tyler
b0f685c2e2
Add files via upload
...
ICache_In_Place
2019-11-08 10:55:08 -05:00
felsabbagh3
58a9140f08
Before evict_wb_old removal
2019-11-07 13:27:38 -05:00
Savan Roshan
e4ee2a9cbd
Parameterization working
2019-11-07 00:14:46 -05:00
Savan Roshan
3a71a2ebdb
Fixed bugs in parameterization
2019-11-06 01:09:30 -05:00
Savan Roshan
8468e7d4d9
Added prefix DCACHE_
2019-11-05 08:33:38 -05:00
Savan Roshan
8264339853
Added Parameterization
2019-11-04 13:20:34 -05:00
felsabbagh3
3b49b82c46
GPR ASIC Working
2019-10-29 23:20:16 -04:00
felsabbagh3
4aa04e76e6
Simulate debug
2019-10-29 14:28:20 -04:00
