wgulian3
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23aabbf01d
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Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
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2020-02-22 20:16:13 -05:00 |
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wgulian3
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f2c0453702
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Add multi-cycle compat module and use it in ALU
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2020-02-21 22:08:09 -05:00 |
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wgulian3
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e76d05f7ce
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Fix issues quartus synthesis issues
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2020-02-18 13:24:18 -05:00 |
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wgulian3
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d71f8fcc73
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Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu.
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2020-02-18 13:02:46 -05:00 |
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wgulian3
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0211ca4add
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Add compat divide module and tb
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2020-02-04 10:59:05 -05:00 |
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wgulian3
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12a4136464
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quartus makefile: Support custom Quartus root location
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2020-01-24 18:42:03 -05:00 |
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