 Blaise Tine
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a06812f93f
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minor updates
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2022-02-01 22:51:33 -05:00 |
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Blaise Tine
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bf72800676
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debug tracing refactoring
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2021-10-17 13:42:16 -07:00 |
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Blaise Tine
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e380ded5e1
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Merge branch 'master' into graphics
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2021-10-15 19:32:11 -07:00 |
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Blaise Tine
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9f34b2944c
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code refactoring for Vivado, sv2v, and yosys compatibility
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2021-09-27 08:55:10 -04:00 |
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Blaise Tine
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bb1ceffadd
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rebase master update
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2021-07-30 21:03:14 -07:00 |
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Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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Blaise Tine
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2d69ca5d67
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scratchpad optimization for stack access using custom bank offset aligned to stack size
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2021-01-02 16:00:00 -05:00 |
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Blaise Tine
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b85391389b
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rename MSRQ to MSHR
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2020-11-28 17:32:00 -05:00 |
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Blaise Tine
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5d58bf3d11
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fixed l3cache hang using memory arbiter in afu
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2020-11-15 06:36:32 -08:00 |
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Blaise Tine
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5be1d85648
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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
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2020-11-02 01:50:12 -08:00 |
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trmontgomery
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0e8b9ec1c2
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read and write complete
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2020-07-13 23:48:51 -04:00 |
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trmontgomery
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e155c8a9b3
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cache makfile changes
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2020-06-30 22:40:14 -04:00 |
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trmontgomery
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9f33a9feb7
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cache_sim.cpp created
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2020-06-30 17:49:43 -04:00 |
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