3 Commits

Author	SHA1	Message	Date
Blaise Tine	4bbd7bf408	performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,	2020-12-19 02:45:06 -08:00
Blaise Tine	1795980a52	L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization	2020-11-21 09:47:56 -08:00
Blaise Tine	83a1695c73	OPAE CSR access	2020-06-30 18:14:06 -07:00