Commit Graph

111 Commits

Author SHA1 Message Date
Blaise Tine
2d48fe13c8 a few fixes... 2021-03-25 14:23:33 -04:00
Blaise Tine
79cbea0a13 tex_unit compiler fixes 2021-03-22 12:20:01 -04:00
Blaise Tine
f499ce6c95 tex_unit memory partial 2021-03-22 10:25:17 -04:00
Blaise Tine
1431ef9bc0 texunit tex_wrap 2021-03-20 13:40:42 -04:00
Blaise Tine
20ae993e51 texunit partial update 2021-03-20 10:50:54 -04:00
Blaise Tine
859877a00d tex_unit partial update 2021-03-20 08:40:57 -04:00
Krishna Yalamarthy
41d7d8e7d5 Point Sampling Tex Unit Update 2021-03-18 16:57:14 -04:00
Blaise Tine
124acfbf12 texture unit dcache arbitration 2021-03-18 14:23:53 -04:00
Blaise Tine
2cbc1c4161 adding texture test to tex_demo 2021-03-17 09:52:33 -04:00
Blaise Tine
676a13f30d tex refactoring and bug fixes 2021-03-16 09:25:57 -04:00
Krishna Yalamarthy
72e06ef4fe Tex CSRs write support added 2021-03-15 16:41:29 -04:00
Krishna Yalamarthy
7587876820 Texture Instruction - Fixed Color 2021-03-15 16:41:28 -04:00
Blaise Tine
8a9a67aa5a minor update 2021-02-27 21:54:55 -08:00
Blaise Tine
f5a17bd1a9 decode optimization and refactoring 2021-02-27 18:21:41 -08:00
Blaise Tine
700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
Blaise Tine
ab63ac9e5d cache request interfaces update 2021-02-10 20:55:04 -08:00
Blaise Tine
fcbf57b66a specialized shared memory module 2021-01-16 04:41:58 -08:00
Blaise Tine
7c4823e65c fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests 2021-01-11 23:55:09 -08:00
Blaise Tine
06945533cf fixed l2/l3 caches related bugs 2021-01-09 16:32:55 -08:00
Blaise Tine
9cef1aae04 cache fill response address is the mshr's top address, no need to store it 2021-01-03 00:57:24 -05:00
Blaise Tine
2d69ca5d67 scratchpad optimization for stack access using custom bank offset aligned to stack size 2021-01-02 16:00:00 -05:00
Blaise Tine
30d950ada2 vx_spawn_warps redesign using opencl's style scheduler 2021-01-01 14:13:48 -05:00
Blaise Tine
138db29310 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2020-12-31 22:40:34 -05:00
Blaise Tine
e4a00dd0d9 fixed loader script stack setup 2020-12-31 22:37:20 -05:00
Blaise Tine
abe32ed553 cache optimization - moved read requests to stage1 and eliminating stage3 2020-12-31 07:40:58 -08:00
Blaise Tine
703a861fe9 added support for write-through cache, removed cache snooping support 2020-12-23 23:51:02 -08:00
Blaise Tine
d5438fd591 merging perf counters 2020-12-08 21:02:39 -08:00
Blaise Tine
268ad15098 minor update 2020-12-06 22:55:17 -08:00
Blaise Tine
1332970636 refactoring cores clustering 2020-12-06 14:42:12 -08:00
Blaise Tine
b2652527bb data/dram bus refactoring 2020-12-06 03:37:22 -08:00
Blaise Tine
f3b1069ce8 adding stream arbiter 2020-12-03 06:40:23 -08:00
Blaise Tine
20f22c7446 scope minor fix 2020-11-22 11:51:46 -08:00
Blaise Tine
1795980a52 L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization 2020-11-21 09:47:56 -08:00
Blaise Tine
5d58bf3d11 fixed l3cache hang using memory arbiter in afu 2020-11-15 06:36:32 -08:00
Blaise Tine
10505caae1 refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2 2020-11-08 01:31:46 -08:00
Blaise Tine
43ae82e788 vlsim fix, verilator fst trace, use ram optimization 2020-10-25 16:40:50 -07:00
Blaise Tine
4e1007e5b2 scope refactoring 2020-10-03 18:53:21 -04:00
Blaise Tine
42e3b6c45d fixed lmp_mult parameters, ram init filepath 2020-09-04 07:51:46 -07:00
Blaise Tine
df711986bc FPU DPI fallback 2020-08-31 09:19:55 -04:00
Blaise Tine
0a0b28aac0 minor update - 206-214 mhz 2020-08-29 05:14:08 -07:00
Blaise Tine
ee81e81818 adding using serial divider to save area cost 2020-08-25 02:29:27 -07:00
Blaise Tine
57971f6c76 decode op_mod optimization 2020-08-24 02:55:14 -07:00
Blaise Tine
0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
Blaise Tine
6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
Blaise Tine
65415d2bbc getting dogfood tests passing on Verilator! 2020-08-09 18:13:12 -04:00
Blaise Tine
cd29362d10 fixed FPU handshake, optimized writeback's critical path 2020-08-07 10:11:54 -07:00
Blaise Tine
ffd9515881 added altera fpu modules 2020-08-05 15:53:59 -07:00
Blaise Tine
31ee824862 merged fpu_port branch 2020-07-31 17:13:22 -04:00
Blaise Tine
836a735555 minor updates 2020-07-31 13:39:52 -07:00
Blaise Tine
c9755a0c48 lkg build with pipeline + FPU fixes 2020-07-31 09:29:44 -04:00