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added altera fpu modules

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This commit is contained in:
Blaise Tine
2020-08-05 15:53:59 -07:00
parent d8bdaa2b4e
commit ffd9515881
48 changed files with 8888 additions and 459 deletions
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28
hw/rtl/libs/VX_shift_register.v
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@@ -2,7 +2,7 @@
module VX_shift_register #(
parameter DATAW = 1,
parameter DEPTH = 0
parameter DEPTH = 1
) (
input wire clk,
input wire reset,
@@ -10,41 +10,33 @@ module VX_shift_register #(
input wire [DATAW-1:0] in,
output wire [DATAW-1:0] out
);
if (0 == DEPTH) begin
reg [DEPTH-1:0][DATAW-1:0] entries;
assign out = in;
end if (1 == DEPTH) begin
reg [DATAW-1:0] ram;
if (1 == DEPTH) begin
always @(posedge clk) begin
if (reset) begin
ram <= '0;
entries <= '0;
end else begin
if (enable) begin
ram <= in;
entries <= in;
end
end
end
assign out = ram;
end else begin
reg [DEPTH-1:0][DATAW-1:0] ram;
end else begin
always @(posedge clk) begin
if (reset) begin
ram <= '0;
entries <= '0;
end else begin
if (enable) begin
ram <= {ram[DEPTH-2:0], in};
entries <= {entries[DEPTH-2:0], in};
end
end
end
assign out = ram [DEPTH-1];
end
assign out = entries [DEPTH-1];
endmodule