wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

added altera fpu modules

Browse Source
This commit is contained in:
Blaise Tine
2020-08-05 15:53:59 -07:00
parent d8bdaa2b4e
commit ffd9515881
48 changed files with 8888 additions and 459 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
hw/rtl/libs/VX_divide.v
View File

@@ -31,7 +31,6 @@ module VX_divide #(
.denom (denom),
.quotient (quotient_unqual),
.remain (remainder_unqual),
.aclr (1'b0),
.clken (clk_en)
);
@@ -41,7 +40,7 @@ module VX_divide #(
divide.lpm_widthd = WIDTHD,
divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_hint = "MAXIMIZE_SPEED=9,LPM_REMAINDERPOSITIVE=FALSE",
divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
divide.lpm_pipeline = PIPELINE;
assign quotient = quotient_unqual [WIDTHQ-1:0];

2
hw/rtl/libs/VX_multiplier.v
View File

@@ -23,8 +23,6 @@ module VX_multiplier #(
.dataa (dataa),
.datab (datab),
.result (result),
.sclr (reset),
.aclr (1'b0),
.clken (clk_en),
.sum (1'b0)
);

28
hw/rtl/libs/VX_shift_register.v
View File

@@ -2,7 +2,7 @@
module VX_shift_register #(
parameter DATAW = 1,
parameter DEPTH = 0
parameter DEPTH = 1
) (
input wire clk,
input wire reset,
@@ -10,41 +10,33 @@ module VX_shift_register #(
input wire [DATAW-1:0] in,
output wire [DATAW-1:0] out
);
if (0 == DEPTH) begin
reg [DEPTH-1:0][DATAW-1:0] entries;
assign out = in;
end if (1 == DEPTH) begin
reg [DATAW-1:0] ram;
if (1 == DEPTH) begin
always @(posedge clk) begin
if (reset) begin
ram <= '0;
entries <= '0;
end else begin
if (enable) begin
ram <= in;
entries <= in;
end
end
end
assign out = ram;
end else begin
reg [DEPTH-1:0][DATAW-1:0] ram;
end else begin
always @(posedge clk) begin
if (reset) begin
ram <= '0;
entries <= '0;
end else begin
if (enable) begin
ram <= {ram[DEPTH-2:0], in};
entries <= {entries[DEPTH-2:0], in};
end
end
end
assign out = ram [DEPTH-1];
end
assign out = entries [DEPTH-1];
endmodule