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added altera fpu modules

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This commit is contained in:
Blaise Tine
2020-08-05 15:53:59 -07:00
parent d8bdaa2b4e
commit ffd9515881
48 changed files with 8888 additions and 459 deletions
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24
hw/rtl/VX_writeback.v
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@@ -25,8 +25,8 @@ module VX_writeback #(
reg [31:0] wb_curr_PC_table [`ISSUEQ_SIZE-1:0];
reg [`NR_BITS-1:0] wb_rd_table [`ISSUEQ_SIZE-1:0];
reg [`ISSUEQ_SIZE-1:0] wb_pending;
reg [`ISSUEQ_SIZE-1:0] wb_pending_n;
reg [`ISSUEQ_SIZE-1:0] wb_valid_table;
reg [`ISSUEQ_SIZE-1:0] wb_valid_table_n;
reg [`ISTAG_BITS-1:0] wb_index;
wire [`ISTAG_BITS-1:0] wb_index_n;
@@ -35,40 +35,40 @@ module VX_writeback #(
wire wb_valid_n;
always @(*) begin
wb_pending_n = wb_pending;
wb_valid_table_n = wb_valid_table;
if (wb_valid) begin
wb_pending_n[wb_index] = 0;
wb_valid_table_n[wb_index] = 0;
end
if (alu_commit_if.valid) begin
wb_pending_n [alu_commit_if.issue_tag] = cmt_to_issue_if.alu_data.wb;
wb_valid_table_n [alu_commit_if.issue_tag] = cmt_to_issue_if.alu_data.wb;
end
if (lsu_commit_if.valid) begin
wb_pending_n [lsu_commit_if.issue_tag] = cmt_to_issue_if.lsu_data.wb;
wb_valid_table_n [lsu_commit_if.issue_tag] = cmt_to_issue_if.lsu_data.wb;
end
if (csr_commit_if.valid) begin
wb_pending_n [csr_commit_if.issue_tag] = cmt_to_issue_if.csr_data.wb;
wb_valid_table_n [csr_commit_if.issue_tag] = cmt_to_issue_if.csr_data.wb;
end
if (mul_commit_if.valid) begin
wb_pending_n [mul_commit_if.issue_tag] = cmt_to_issue_if.mul_data.wb;
wb_valid_table_n [mul_commit_if.issue_tag] = cmt_to_issue_if.mul_data.wb;
end
if (fpu_commit_if.valid) begin
wb_pending_n [fpu_commit_if.issue_tag] = cmt_to_issue_if.fpu_data.wb;
wb_valid_table_n [fpu_commit_if.issue_tag] = cmt_to_issue_if.fpu_data.wb;
end
end
VX_priority_encoder #(
.N(`ISSUEQ_SIZE)
) wb_select (
.data_in (wb_pending_n),
.data_in (wb_valid_table_n),
.data_out (wb_index_n),
.valid_out (wb_valid_n)
);
always @(posedge clk) begin
if (reset) begin
wb_pending <= 0;
wb_valid_table <= 0;
wb_index <= 0;
wb_valid <= 0;
end else begin
@@ -112,7 +112,7 @@ module VX_writeback #(
wb_rd_table [fpu_commit_if.issue_tag] <= cmt_to_issue_if.fpu_data.rd;
end
wb_pending <= wb_pending_n;
wb_valid_table <= wb_valid_table_n;
wb_index <= wb_index_n;
wb_valid <= wb_valid_n && writeback_if.ready;
end