added altera fpu modules

hw/rtl/VX_define.vh

@@ -38,9 +38,16 @@
 
 ///////////////////////////////////////////////////////////////////////////////
 
-`define LATENCY_IDIV    24
+`define LATENCY_IDIV    22
 `define LATENCY_IMUL    2
 
+`define LATENCY_FDIV     16
+`define LATENCY_FSQRT    10
+`define LATENCY_FTOI     5
+`define LATENCY_FTOU     4
+`define LATENCY_ITOF     8
+`define LATENCY_UTOF     7
+
 `define LATENCY_FMULADD  2
 `define LATENCY_FDIVSQRT 2
 `define LATENCY_FCONV    2
@@ -193,6 +200,12 @@
 `define FRM_RMM    3'b100  // round to nearest max magnitude
 `define FRM_DYN    3'b111  // dynamic mode
 `define FRM_BITS   3
+
+`define FFG_NX     0 // inexact
+`define FFG_UF     1 // underflow 
+`define FFG_OF     2 // overflow
+`define FFG_DZ     3 // division by zero
+`define FFG_NV     4 // invalid
 `define FFG_BITS   5
 
 `define GPU_TMC     3'h0
@@ -415,6 +428,16 @@ typedef struct packed {
     logic [31:0]            curr_PC;
     logic [`NR_BITS-1:0]    rd;
     logic                   wb;
-} is_data_t;
+} issue_data_t;
+
+typedef struct packed {
+    logic is_normal;
+    logic is_zero;
+    logic is_subnormal;
+    logic is_inf;
+    logic is_nan;
+    logic is_signaling;
+    logic is_quiet;
+} fp_type_t;
 
 `endif