Optimized cache writeback path by 1) VX_fair_arbiter and 2) Added a wb register between LSU and WB arbiter

2020-06-28 14:27:47 -07:00
parent c95d3cb22b
commit ffb760cf73
4 changed files with 91 additions and 7 deletions
--- a/hw/rtl/VX_back_end.v
+++ b/hw/rtl/VX_back_end.v
@@ -76,7 +76,7 @@ module VX_back_end #(
        .clk            (clk),
        .reset          (reset),
        .lsu_req_if     (lsu_req_if),
-        .mem_wb_if      (mem_wb_if),
+        .mem_wb_if_p1   (mem_wb_if),
        .dcache_req_if  (dcache_req_if),
        .dcache_rsp_if  (dcache_rsp_if),
        .delay          (mem_delay),
@@ -145,4 +145,4 @@ module VX_back_end #(
    `SCOPE_ASSIGN(scope_writeback_rd,       writeback_if.rd);
    `SCOPE_ASSIGN(scope_writeback_data,     writeback_if.data);

-endmodule
+endmodule