opae build fixes

hw/opae/Makefile

@@ -4,13 +4,16 @@ FPGA_BUILD_DIR=build_fpga
 
 all: ase-1c
 
-ase-1c: setup-ase-1c
+sources.txt: 
+	./gen_sources.sh
+
+ase-1c: setup-ase-1c sources.txt
 	make -C $(ASE_BUILD_DIR)_1c
 
-ase-2c: setup-ase-2c
+ase-2c: setup-ase-2c sources.txt
 	make -C $(ASE_BUILD_DIR)_2c
 
-ase-4c: setup-ase-4c
+ase-4c: setup-ase-4c sources.txt
 	make -C $(ASE_BUILD_DIR)_4c
 
 setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
@@ -28,13 +31,13 @@ $(ASE_BUILD_DIR)_2c/Makefile:
 $(ASE_BUILD_DIR)_4c/Makefile:
 	afu_sim_setup -s sources_4c.txt $(ASE_BUILD_DIR)_4c
 
-fpga-1c: setup-fpga-1c
+fpga-1c: setup-fpga-1c sources.txt
 	cd $(FPGA_BUILD_DIR)_1c && qsub-synth
 
-fpga-2c: setup-fpga-2c
+fpga-2c: setup-fpga-2c sources.txt
 	cd $(FPGA_BUILD_DIR)_2c && qsub-synth
 
-fpga-4c: setup-fpga-4c
+fpga-4c: setup-fpga-4c sources.txt
 	cd $(FPGA_BUILD_DIR)_4c && qsub-synth
 	
 setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf

hw/opae/README

@@ -60,8 +60,8 @@ qsub-sim
 make ase
 
 # tests
-./run_ase.sh build_ase_1c ../../driver/tests/basic/basic
-./run_ase.sh build_ase_1c ../../driver/tests/demo/demo
+./run_ase.sh build_ase_1c ../../driver/tests/basic/basic -n 256
+./run_ase.sh build_ase_1c ../../driver/tests/demo/demo -n 16
 ./run_ase.sh build_ase_1c ../../benchmarks/opencl/vecadd/vecadd
 
 # modify "vsim_run.tcl" to dump VCD trace

hw/opae/gen_sources.sh

@@ -0,0 +1,21 @@
+#!/bin/bash
+
+dir_list='../rtl/libs ../rtl/cache ../rtl/interfaces ../rtl'
+
+inc_list=""
+for dir in $dir_list; do
+	inc_list="$inc_list -I$dir"
+done
+
+echo "inc_list=$inc_list"
+
+{
+    # read design sources
+    for dir in $dir_list; do
+        echo "+incdir+$dir"
+        for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f) 
+        do
+            echo $file
+        done
+    done
+} > sources.txt

hw/opae/sources.txt

@@ -1,46 +1,34 @@
-vortex_afu.json
-
-QI:vortex_afu.qsf
-
-#+define+SCOPE
-
-#+define+DBG_PRINT_CORE_ICACHE
-#+define+DBG_PRINT_CORE_DCACHE
-#+define+DBG_PRINT_CACHE_BANK
-#+define+DBG_PRINT_CACHE_SNP
-#+define+DBG_PRINT_CACHE_MSRQ
-#+define+DBG_PRINT_DRAM
-#+define+DBG_PRINT_PIPELINE
-#+define+DBG_PRINT_OPAE
-#+define+DBG_PRINT_SCOPE
-
-+incdir+.
-+incdir+../rtl
-+incdir+../rtl/interfaces
-+incdir+../rtl/pipe_regs
-+incdir+../rtl/cache
 +incdir+../rtl/libs
-
-../rtl/VX_user_config.vh
-../rtl/VX_config.vh
-../rtl/VX_define.vh
-
-../rtl/cache/VX_cache_config.vh
-../rtl/cache/VX_cache.v
-../rtl/cache/VX_cache_core_rsp_merge.v
-../rtl/cache/VX_cache_core_req_bank_sel.v
-../rtl/cache/VX_cache_dram_req_arb.v
-../rtl/cache/VX_cache_dram_fill_arb.v
-../rtl/cache/VX_cache_miss_resrv.v
+../rtl/libs/VX_countones.v
+../rtl/libs/VX_divide.v
+../rtl/libs/VX_fair_arbiter.v
+../rtl/libs/VX_fixed_arbiter.v
+../rtl/libs/VX_generic_queue.v
+../rtl/libs/VX_generic_register.v
+../rtl/libs/VX_generic_stack.v
+../rtl/libs/VX_index_queue.v
+../rtl/libs/VX_matrix_arbiter.v
+../rtl/libs/VX_mult.v
+../rtl/libs/VX_priority_encoder.v
+../rtl/libs/VX_rr_arbiter.v
+../rtl/libs/VX_onehot_encooder.v
++incdir+../rtl/cache
 ../rtl/cache/VX_bank.v
 ../rtl/cache/VX_bank_core_req_arb.v
+../rtl/cache/VX_cache.v
+../rtl/cache/VX_cache_core_req_bank_sel.v
+../rtl/cache/VX_cache_core_rsp_merge.v
+../rtl/cache/VX_cache_dram_fill_arb.v
+../rtl/cache/VX_cache_dram_req_arb.v
+../rtl/cache/VX_cache_miss_resrv.v
+../rtl/cache/VX_prefetcher.v
+../rtl/cache/VX_snp_forwarder.v
 ../rtl/cache/VX_snp_rsp_arb.v
 ../rtl/cache/VX_tag_data_access.v
 ../rtl/cache/VX_tag_data_structure.v
-../rtl/cache/VX_snp_forwarder.v
-../rtl/cache/VX_prefetcher.v
-
-../rtl/interfaces/VX_branch_rsp_if.v
++incdir+../rtl/interfaces
+../rtl/interfaces/VX_alu_req_if.v
+../rtl/interfaces/VX_branch_ctl_if.v
 ../rtl/interfaces/VX_cache_core_req_if.v
 ../rtl/interfaces/VX_cache_core_rsp_if.v
 ../rtl/interfaces/VX_cache_dram_req_if.v
@@ -48,65 +36,46 @@ QI:vortex_afu.qsf
 ../rtl/interfaces/VX_cache_snp_req_if.v
 ../rtl/interfaces/VX_cache_snp_rsp_if.v
 ../rtl/interfaces/VX_csr_req_if.v
+../rtl/interfaces/VX_commit_if.v
 ../rtl/interfaces/VX_csr_io_req_if.v
-../rtl/interfaces/VX_csr_io_rsp_if.v
-../rtl/interfaces/VX_exec_unit_req_if.v
-../rtl/interfaces/VX_backend_req_if.v
-../rtl/interfaces/VX_gpr_read_if.v
-../rtl/interfaces/VX_gpu_inst_req_if.v
-../rtl/interfaces/VX_inst_meta_if.v
-../rtl/interfaces/VX_jal_rsp_if.v
+../rtl/interfaces/VX_decode_if.v
+../rtl/interfaces/VX_gpr_data_if.v
+../rtl/interfaces/VX_gpu_req_if.v
 ../rtl/interfaces/VX_join_if.v
 ../rtl/interfaces/VX_lsu_req_if.v
 ../rtl/interfaces/VX_warp_ctl_if.v
 ../rtl/interfaces/VX_wb_if.v
 ../rtl/interfaces/VX_wstall_if.v
-
-../rtl/libs/VX_generic_register.v
-../rtl/libs/VX_mult.v
-../rtl/libs/VX_divide.v
-../rtl/libs/VX_generic_stack.v
-../rtl/libs/VX_priority_encoder.v
-../rtl/libs/VX_generic_queue.v
-../rtl/libs/VX_indexable_queue.v
-../rtl/libs/VX_fair_arbiter.v
-../rtl/libs/VX_fixed_arbiter.v
-../rtl/libs/VX_rr_arbiter.v
-../rtl/libs/VX_countones.v
-../rtl/libs/VX_scope.v
-
-../rtl/Vortex.v
+../rtl/interfaces/VX_csr_io_rsp_if.v
+../rtl/interfaces/VX_ifetch_req_if.v
+../rtl/interfaces/VX_ifetch_rsp_if.v
+../rtl/interfaces/VX_mul_req_if.v
+../rtl/interfaces/VX_perf_cntrs_if.v
++incdir+../rtl
+../rtl/VX_alu_unit.v
+../rtl/VX_commit.v
 ../rtl/VX_cluster.v
 ../rtl/VX_core.v
-../rtl/VX_mem_unit.v
-../rtl/VX_pipeline.v
-../rtl/VX_front_end.v
-../rtl/VX_back_end.v
-../rtl/VX_fetch.v
-../rtl/VX_scheduler.v
-../rtl/VX_exec_unit.v
-../rtl/VX_warp.v
-../rtl/VX_icache_stage.v
-../rtl/VX_gpr_wrapper.v
-../rtl/VX_gpu_inst.v
-../rtl/VX_writeback.v
-../rtl/VX_csr_pipe.v
 ../rtl/VX_csr_data.v
 ../rtl/VX_csr_arb.v
+../rtl/VX_dcache_arb.v
+../rtl/VX_decode.v
 ../rtl/VX_csr_io_arb.v
-../rtl/VX_warp_sched.v
+../rtl/VX_fetch.v
+../rtl/VX_csr_unit.v
 ../rtl/VX_gpr_ram.v
 ../rtl/VX_gpr_stage.v
-../rtl/VX_alu_unit.v
+../rtl/VX_execute.v
+../rtl/VX_gpu_unit.v
+../rtl/VX_icache_stage.v
+../rtl/VX_issue.v
 ../rtl/VX_lsu_unit.v
-../rtl/VX_decode.v
-../rtl/VX_inst_multiplex.v
-../rtl/VX_dcache_arb.v
 ../rtl/VX_mem_arb.v
-../rtl/VX_f_d_reg.v
-../rtl/VX_i_d_reg.v
-../rtl/VX_d_e_reg.v
-
-ccip_interface_reg.sv
-ccip_std_afu.sv
-vortex_afu.sv
+../rtl/VX_mem_unit.v
+../rtl/VX_pipeline.v
+../rtl/VX_scheduler.v
+../rtl/VX_issue_mux.v
+../rtl/VX_warp_sched.v
+../rtl/VX_writeback.v
+../rtl/Vortex.v
+../rtl/VX_mul_unit.v

hw/opae/sources_1c.txt

@@ -1,3 +1,21 @@
 +define+NUM_CORES=1
 
+#+define+SCOPE
+
+#+define+DBG_PRINT_CORE_ICACHE
+#+define+DBG_PRINT_CORE_DCACHE
+#+define+DBG_PRINT_CACHE_BANK
+#+define+DBG_PRINT_CACHE_SNP
+#+define+DBG_PRINT_CACHE_MSRQ
+#+define+DBG_PRINT_DRAM
+#+define+DBG_PRINT_PIPELINE
+#+define+DBG_PRINT_OPAE
+#+define+DBG_PRINT_SCOPE
+
+vortex_afu.json
+QI:vortex_afu.qsf
+ccip_interface_reg.sv
+ccip_std_afu.sv
+vortex_afu.sv
+
 C:sources.txt

hw/opae/sources_2c.txt

@@ -1,4 +1,10 @@
 +define+NUM_CORES=2
 +define+L2_ENABLE=0
 
+vortex_afu.json
+QI:vortex_afu.qsf
+ccip_interface_reg.sv
+ccip_std_afu.sv
+vortex_afu.sv
+
 C:sources.txt

hw/opae/sources_4c.txt

@@ -1,4 +1,10 @@
 +define+NUM_CORES=4
 +define+L2_ENABLE=0
 
+vortex_afu.json
+QI:vortex_afu.qsf
+ccip_interface_reg.sv
+ccip_std_afu.sv
+vortex_afu.sv
+
 C:sources.txt