wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

dispatch refactoring

Browse Source
This commit is contained in:
Blaise Tine
2021-10-19 15:16:00 -04:00
parent 5423958366
commit fe862f64b1
7 changed files with 69 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hw/rtl/VX_instr_demux.sv → hw/rtl/VX_dispatch.sv
View File

@@ -1,6 +1,6 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_instr_demux ( module VX_dispatch (
input wire clk, input wire clk,
input wire reset, input wire reset,

114
hw/rtl/VX_issue.sv
View File

@@ -23,56 +23,60 @@ module VX_issue #(
`endif `endif
VX_gpu_req_if.master gpu_req_if VX_gpu_req_if.master gpu_req_if
); );
VX_ibuffer_if ibuffer_if(); VX_ibuffer_if ibuffer_if();
VX_gpr_rsp_if gpr_rsp_if(); VX_gpr_req_if gpr_req_if();
VX_gpr_rsp_if gpr_rsp_if();
VX_gpr_req_if gpr_req_if();
assign gpr_req_if.wid = ibuffer_if.wid;
assign gpr_req_if.rs1 = ibuffer_if.rs1;
assign gpr_req_if.rs2 = ibuffer_if.rs2;
assign gpr_req_if.rs3 = ibuffer_if.rs3;
VX_writeback_if sboard_wb_if(); VX_writeback_if sboard_wb_if();
assign sboard_wb_if.valid = writeback_if.valid; VX_ibuffer_if scoreboard_if();
assign sboard_wb_if.wid = writeback_if.wid; VX_ibuffer_if dispatch_if();
assign sboard_wb_if.PC = writeback_if.PC;
assign sboard_wb_if.rd = writeback_if.rd;
assign sboard_wb_if.eop = writeback_if.eop;
assign sboard_wb_if.ready = writeback_if.ready;
VX_ibuffer_if sboard_ib_if();
assign sboard_ib_if.valid = ibuffer_if.valid && idmux_ib_if.ready;
assign sboard_ib_if.wid = ibuffer_if.wid;
assign sboard_ib_if.PC = ibuffer_if.PC;
assign sboard_ib_if.wb = ibuffer_if.wb;
assign sboard_ib_if.rd = ibuffer_if.rd;
assign sboard_ib_if.rd_n = ibuffer_if.rd_n;
assign sboard_ib_if.rs1_n = ibuffer_if.rs1_n;
assign sboard_ib_if.rs2_n = ibuffer_if.rs2_n;
assign sboard_ib_if.rs3_n = ibuffer_if.rs3_n;
assign sboard_ib_if.wid_n = ibuffer_if.wid_n;
VX_ibuffer_if idmux_ib_if(); // GPR request interface
assign idmux_ib_if.valid = ibuffer_if.valid && sboard_ib_if.ready; assign gpr_req_if.wid = ibuffer_if.wid;
assign idmux_ib_if.wid = ibuffer_if.wid; assign gpr_req_if.rs1 = ibuffer_if.rs1;
assign idmux_ib_if.tmask = ibuffer_if.tmask; assign gpr_req_if.rs2 = ibuffer_if.rs2;
assign idmux_ib_if.PC = ibuffer_if.PC; assign gpr_req_if.rs3 = ibuffer_if.rs3;
assign idmux_ib_if.ex_type = ibuffer_if.ex_type;
assign idmux_ib_if.op_type = ibuffer_if.op_type; // scoreboard writeback interface
assign idmux_ib_if.op_mod = ibuffer_if.op_mod; assign sboard_wb_if.valid = writeback_if.valid;
assign idmux_ib_if.wb = ibuffer_if.wb; assign sboard_wb_if.wid = writeback_if.wid;
assign idmux_ib_if.rd = ibuffer_if.rd; assign sboard_wb_if.PC = writeback_if.PC;
assign idmux_ib_if.rs1 = ibuffer_if.rs1; assign sboard_wb_if.rd = writeback_if.rd;
assign idmux_ib_if.imm = ibuffer_if.imm; assign sboard_wb_if.eop = writeback_if.eop;
assign idmux_ib_if.use_PC = ibuffer_if.use_PC;
assign idmux_ib_if.use_imm = ibuffer_if.use_imm; // scoreboard interface
assign scoreboard_if.valid = ibuffer_if.valid && dispatch_if.ready;
assign scoreboard_if.wid = ibuffer_if.wid;
assign scoreboard_if.PC = ibuffer_if.PC;
assign scoreboard_if.wb = ibuffer_if.wb;
assign scoreboard_if.rd = ibuffer_if.rd;
assign scoreboard_if.rd_n = ibuffer_if.rd_n;
assign scoreboard_if.rs1_n = ibuffer_if.rs1_n;
assign scoreboard_if.rs2_n = ibuffer_if.rs2_n;
assign scoreboard_if.rs3_n = ibuffer_if.rs3_n;
assign scoreboard_if.wid_n = ibuffer_if.wid_n;
// dispatch interface
assign dispatch_if.valid = ibuffer_if.valid && scoreboard_if.ready;
assign dispatch_if.wid = ibuffer_if.wid;
assign dispatch_if.tmask = ibuffer_if.tmask;
assign dispatch_if.PC = ibuffer_if.PC;
assign dispatch_if.ex_type = ibuffer_if.ex_type;
assign dispatch_if.op_type = ibuffer_if.op_type;
assign dispatch_if.op_mod = ibuffer_if.op_mod;
assign dispatch_if.wb = ibuffer_if.wb;
assign dispatch_if.rd = ibuffer_if.rd;
assign dispatch_if.rs1 = ibuffer_if.rs1;
assign dispatch_if.imm = ibuffer_if.imm;
assign dispatch_if.use_PC = ibuffer_if.use_PC;
assign dispatch_if.use_imm = ibuffer_if.use_imm;
// issue the instruction // issue the instruction
assign ibuffer_if.ready = sboard_ib_if.ready && idmux_ib_if.ready; assign ibuffer_if.ready = scoreboard_if.ready && dispatch_if.ready;
`RESET_RELAY (ibuf_reset); `RESET_RELAY (ibuf_reset);
`RESET_RELAY (scoreboard_reset);
`RESET_RELAY (gpr_reset); `RESET_RELAY (gpr_reset);
`RESET_RELAY (demux_reset); `RESET_RELAY (dispatch_reset);
VX_ibuffer #( VX_ibuffer #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
@@ -87,9 +91,9 @@ module VX_issue #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
) scoreboard ( ) scoreboard (
.clk (clk), .clk (clk),
.reset (reset), .reset (scoreboard_reset),
.ibuffer_if (sboard_ib_if), .writeback_if(sboard_wb_if),
.writeback_if(sboard_wb_if) .ibuffer_if (scoreboard_if)
); );
VX_gpr_stage #( VX_gpr_stage #(
@@ -102,10 +106,10 @@ module VX_issue #(
.gpr_rsp_if (gpr_rsp_if) .gpr_rsp_if (gpr_rsp_if)
); );
VX_instr_demux instr_demux ( VX_dispatch dispatch (
.clk (clk), .clk (clk),
.reset (demux_reset), .reset (dispatch_reset),
.ibuffer_if (idmux_ib_if), .ibuffer_if (dispatch_if),
.gpr_rsp_if (gpr_rsp_if), .gpr_rsp_if (gpr_rsp_if),
.alu_req_if (alu_req_if), .alu_req_if (alu_req_if),
.lsu_req_if (lsu_req_if), .lsu_req_if (lsu_req_if),
@@ -131,11 +135,11 @@ module VX_issue #(
`SCOPE_ASSIGN (issue_imm, ibuffer_if.imm); `SCOPE_ASSIGN (issue_imm, ibuffer_if.imm);
`SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC); `SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC);
`SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm); `SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm);
`SCOPE_ASSIGN (scoreboard_delay, !sboard_wb_if.ready); `SCOPE_ASSIGN (scoreboard_delay, !scoreboard_if.ready);
`SCOPE_ASSIGN (execute_delay, !idmux_ib_if.ready); `SCOPE_ASSIGN (dispatch_delay, !dispatch_if.ready);
`SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data); `SCOPE_ASSIGN (gpr_rs1, gpr_rsp_if.rs1_data);
`SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data); `SCOPE_ASSIGN (gpr_rs2, gpr_rsp_if.rs2_data);
`SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data); `SCOPE_ASSIGN (gpr_rs3, gpr_rsp_if.rs3_data);
`SCOPE_ASSIGN (writeback_valid, writeback_if.valid); `SCOPE_ASSIGN (writeback_valid, writeback_if.valid);
`SCOPE_ASSIGN (writeback_tmask, writeback_if.tmask); `SCOPE_ASSIGN (writeback_tmask, writeback_if.tmask);
`SCOPE_ASSIGN (writeback_wid, writeback_if.wid); `SCOPE_ASSIGN (writeback_wid, writeback_if.wid);
@@ -170,7 +174,7 @@ module VX_issue #(
if (decode_if.valid & !decode_if.ready) begin if (decode_if.valid & !decode_if.ready) begin
perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1; perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1;
end end
if (ibuffer_if.valid & !sboard_wb_if.ready) begin if (scoreboard_if.valid & !scoreboard_if.ready) begin
perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1; perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1;
end end
if (alu_req_if.valid & !alu_req_if.ready) begin if (alu_req_if.valid & !alu_req_if.ready) begin

5
hw/rtl/VX_scoreboard.sv
View File

@@ -6,8 +6,8 @@ module VX_scoreboard #(
input wire clk, input wire clk,
input wire reset, input wire reset,
VX_ibuffer_if.scoreboard ibuffer_if, VX_ibuffer_if.slave ibuffer_if,
VX_writeback_if.scoreboard writeback_if VX_writeback_if.slave writeback_if
); );
reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n; reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n;
@@ -53,6 +53,7 @@ module VX_scoreboard #(
reg [31:0] deadlock_ctr; reg [31:0] deadlock_ctr;
wire [31:0] deadlock_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); wire [31:0] deadlock_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
deadlock_ctr <= 0; deadlock_ctr <= 0;

14
hw/rtl/interfaces/VX_ibuffer_if.sv
View File

@@ -76,20 +76,6 @@ interface VX_ibuffer_if ();
input wid_n, input wid_n,
output ready output ready
); );
modport scoreboard (
input valid,
input wid,
input PC,
input wb,
input rd,
input rd_n,
input rs1_n,
input rs2_n,
input rs3_n,
input wid_n,
output ready
);
endinterface endinterface

9
hw/rtl/interfaces/VX_writeback_if.sv
View File

@@ -36,15 +36,6 @@ interface VX_writeback_if ();
output ready output ready
); );
modport scoreboard (
input valid,
input wid,
input PC,
input rd,
input eop,
output ready
);
endinterface endinterface
`endif `endif

8
hw/scripts/scope.json
View File

@@ -194,9 +194,9 @@
"issue_imm": 32, "issue_imm": 32,
"issue_use_pc": 1, "issue_use_pc": 1,
"issue_use_imm": 1, "issue_use_imm": 1,
"gpr_rsp_a":"`NUM_THREADS * 32", "gpr_rs1":"`NUM_THREADS * 32",
"gpr_rsp_b":"`NUM_THREADS * 32", "gpr_rs2":"`NUM_THREADS * 32",
"gpr_rsp_c":"`NUM_THREADS * 32", "gpr_rs3":"`NUM_THREADS * 32",
"?writeback_valid": 1, "?writeback_valid": 1,
"writeback_wid":"`NW_BITS", "writeback_wid":"`NW_BITS",
"writeback_pc": 32, "writeback_pc": 32,
@@ -205,7 +205,7 @@
"writeback_data":"`NUM_THREADS * 32", "writeback_data":"`NUM_THREADS * 32",
"writeback_eop": 1, "writeback_eop": 1,
"!scoreboard_delay": 1, "!scoreboard_delay": 1,
"!execute_delay": 1 "!dispatch_delay": 1
}, },
"afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank": { "afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank": {
"?valid_st0": 1, "?valid_st0": 1,

4
sim/vlsim/Makefile
View File

@@ -86,12 +86,12 @@ VL_FLAGS += -D$(FPU_CORE)
PROJECT = libopae-c-vlsim PROJECT = libopae-c-vlsim
all: shared all: $(PROJECT).so
vortex_afu.h : $(RTL_DIR)/afu/vortex_afu.vh vortex_afu.h : $(RTL_DIR)/afu/vortex_afu.vh
$(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/afu/vortex_afu.vh -o vortex_afu.h $(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/afu/vortex_afu.vh -o vortex_afu.h
shared: $(SRCS) vortex_afu.h $(PROJECT).so: $(SRCS) vortex_afu.h
verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT).so verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT).so
static: $(SRCS) vortex_afu.h static: $(SRCS) vortex_afu.h