synchronous reset network optimization: only reset register when required

2020-11-11 20:54:54 -08:00
parent ce95c40aee
commit fceb561cbd
8 changed files with 11 additions and 20 deletions
--- a/hw/rtl/VX_ibuffer.v
+++ b/hw/rtl/VX_ibuffer.v
@@ -20,7 +20,7 @@ module VX_ibuffer #(
    localparam ADDRW   = $clog2(SIZE);
    localparam NWARPSW = $clog2(`NUM_WARPS+1);

-    reg [SIZEW-1:0] size_r [`NUM_WARPS-1:0];
+    reg [`NUM_WARPS-1:0][SIZEW-1:0] size_r;
    
    wire [`NUM_WARPS-1:0] q_full;
    wire [`NUM_WARPS-1:0][SIZEW-1:0] q_size;