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This commit is contained in:
Blaise Tine
2020-04-14 06:35:20 -04:00
parent 1de06fd9c0
commit fc155e1223
1056 changed files with 8120 additions and 8120 deletions
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rtl/.DS_Store vendored
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rtl/.gitignore vendored
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/simulate/VX_define.h
/simulate/VX_define_synth.h
/VX_define_synth.v
/results.txt

85
rtl/Makefile
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all: RUNFILE
INCLUDE = -I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate
SINGLE_CORE = Vortex.v
MULTI_CORE = Vortex_SOC.v
EXE += --exe ./simulate/test_bench.cpp ./simulate/simulator.cpp
VF += -compiler gcc --language 1800-2009
WNO += -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN
# WNO=
# LIGHTW=
LIGHTW += -Wno-UNOPTFLAT
# LIB=-LDFLAGS '-L/usr/local/systemc/'
LIB +=
CF += -std=c++11 -fms-extensions
DEB += --trace -DVL_DEBUG=1
MAKECPP += (cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
MAKECPPRel += (cd obj_dir && make -j -f VVortex.mk)
MAKEMULTICPP += (cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
.PHONY: build_config
build_config:
./gen_config.py --rtl_locations
# -LDFLAGS '-lsystemc'
VERILATOR: build_config
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(LIGHTW)
VERILATORnoWarnings: build_config
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(WNO) $(DEB)
VERILATORnoWarningsRel: build_config
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) --threads $(THREADS)
VERILATORMULTInoWarnings: build_config
verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DUSE_MULTICORE' $(WNO) $(DEB)
compdebug: build_config
verilator_bin_dbg $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
compdebugmulti: build_config
verilator_bin_dbg $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DUSE_MULTICORE -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
RUNFILE: VERILATOR
$(MAKECPP)
debug: compdebug
$(MAKECPP)
w: VERILATORnoWarnings
$(MAKECPP)
wRel: VERILATORnoWarningsRel
$(MAKECPPRel)
multicore: VERILATORMULTInoWarnings
$(MAKEMULTICPP)
dmulticore: compdebugmulti
$(MAKEMULTICPP)
run: w
(cd obj_dir && ./VVortex)
run-multicore: multicore
(cd obj_dir && ./VVortex_SOC)
runRel: wRel
(cd obj_dir && ./VVortex)
clean:
rm -rf obj_dir

209
rtl/VX_alu.v
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`include "VX_define.v"
module VX_alu(
input wire clk,
input wire reset,
input wire[31:0] in_1,
input wire[31:0] in_2,
input wire in_rs2_src,
input wire[31:0] in_itype_immed,
input wire[19:0] in_upper_immed,
input wire[4:0] in_alu_op,
input wire[31:0] in_curr_PC,
output reg[31:0] out_alu_result,
output reg out_alu_stall
);
localparam div_pipeline_len = 20;
localparam mul_pipeline_len = 8;
wire[31:0] unsigned_div_result;
wire[31:0] unsigned_rem_result;
wire[31:0] signed_div_result;
wire[31:0] signed_rem_result;
wire[63:0] mul_data_a, mul_data_b;
wire[63:0] mul_result;
wire[31:0] ALU_in1;
wire[31:0] ALU_in2;
VX_divide #(
.WIDTHN(32),
.WIDTHD(32),
.SPEED("HIGHEST"),
.PIPELINE(div_pipeline_len)
) unsigned_div (
.clock(clk),
.aclr(1'b0),
.clken(1'b1), // TODO this could be disabled on inactive instructions
.numer(ALU_in1),
.denom(ALU_in2),
.quotient(unsigned_div_result),
.remainder(unsigned_rem_result)
);
VX_divide #(
.WIDTHN(32),
.WIDTHD(32),
.NREP("SIGNED"),
.DREP("SIGNED"),
.SPEED("HIGHEST"),
.PIPELINE(div_pipeline_len)
) signed_div (
.clock(clk),
.aclr(1'b0),
.clken(1'b1), // TODO this could be disabled on inactive instructions
.numer(ALU_in1),
.denom(ALU_in2),
.quotient(signed_div_result),
.remainder(signed_rem_result)
);
VX_mult #(
.WIDTHA(64),
.WIDTHB(64),
.WIDTHP(64),
.SPEED("HIGHEST"),
.FORCE_LE("YES"),
.PIPELINE(mul_pipeline_len)
) multiplier (
.clock(clk),
.aclr(1'b0),
.clken(1'b1), // TODO this could be disabled on inactive instructions
.dataa(mul_data_a),
.datab(mul_data_b),
.result(mul_result)
);
// MUL, MULH (signed*signed), MULHSU (signed*unsigned), MULHU (unsigned*unsigned)
wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1};
wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2};
assign mul_data_a = (in_alu_op == `MULHU) ? {32'b0, ALU_in1} : alu_in1_signed;
assign mul_data_b = (in_alu_op == `MULHU || in_alu_op == `MULHSU) ? {32'b0, ALU_in2} : alu_in2_signed;
reg [15:0] curr_inst_delay;
reg [15:0] inst_delay;
reg inst_was_stalling;
wire inst_delay_stall = inst_was_stalling ? inst_delay != 0 : curr_inst_delay != 0;
assign out_alu_stall = inst_delay_stall;
always @(*) begin
case(in_alu_op)
`DIV,
`DIVU,
`REM,
`REMU: curr_inst_delay = div_pipeline_len;
`MUL,
`MULH,
`MULHSU,
`MULHU: curr_inst_delay = mul_pipeline_len;
default: curr_inst_delay = 0;
endcase // in_alu_op
end
always @(posedge clk or posedge reset) begin
if (reset) begin
inst_delay <= 0;
inst_was_stalling <= 0;
end
else if (inst_delay_stall) begin
if (inst_was_stalling) begin
if (inst_delay > 0)
inst_delay <= inst_delay - 1;
end
else begin
inst_was_stalling <= 1;
inst_delay <= curr_inst_delay - 1;
end
end
else begin
inst_was_stalling <= 0;
end
end
`ifdef SYN_FUNC
wire which_in2;
wire[31:0] upper_immed;
assign which_in2 = in_rs2_src == `RS2_IMMED;
assign ALU_in1 = in_1;
assign ALU_in2 = which_in2 ? in_itype_immed : in_2;
assign upper_immed = {in_upper_immed, {12{1'b0}}};
always @(*) begin
case(in_alu_op)
`ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);
`SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0];
`SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
`SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
`XOR: out_alu_result = ALU_in1 ^ ALU_in2;
`SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0];
`SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0];
`OR: out_alu_result = ALU_in1 | ALU_in2;
`AND: out_alu_result = ALU_in2 & ALU_in1;
`SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
`LUI_ALU: out_alu_result = upper_immed;
`AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
`MUL: out_alu_result = mul_result[31:0];
`MULH: out_alu_result = mul_result[63:32];
`MULHSU: out_alu_result = mul_result[63:32];
`MULHU: out_alu_result = mul_result[63:32];
`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
`REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result;
default: out_alu_result = 32'h0;
endcase // in_alu_op
end
`else
wire which_in2;
wire[31:0] upper_immed;
assign which_in2 = in_rs2_src == `RS2_IMMED;
assign ALU_in1 = in_1;
assign ALU_in2 = which_in2 ? in_itype_immed : in_2;
assign upper_immed = {in_upper_immed, {12{1'b0}}};
always @(*) begin
case(in_alu_op)
`ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);
`SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0];
`SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
`SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
`XOR: out_alu_result = ALU_in1 ^ ALU_in2;
`SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0];
`SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0];
`OR: out_alu_result = ALU_in1 | ALU_in2;
`AND: out_alu_result = ALU_in2 & ALU_in1;
`SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
`LUI_ALU: out_alu_result = upper_immed;
`AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
`MUL: out_alu_result = mul_result[31:0];
`MULH: out_alu_result = mul_result[63:32];
`MULHSU: out_alu_result = mul_result[63:32];
`MULHU: out_alu_result = mul_result[63:32];
`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
`REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result;
default: out_alu_result = 32'h0;
endcase // in_alu_op
end
`endif
endmodule : VX_alu

142
rtl/VX_back_end.v
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`include "VX_define.v"
module VX_back_end
#(
parameter CORE_ID = 0
)
(
input wire clk,
input wire reset,
input wire schedule_delay,
VX_gpu_dcache_res_inter VX_dcache_rsp,
VX_gpu_dcache_req_inter VX_dcache_req,
output wire out_mem_delay,
output wire out_exec_delay,
output wire gpr_stage_delay,
VX_jal_response_inter VX_jal_rsp,
VX_branch_response_inter VX_branch_rsp,
VX_frE_to_bckE_req_inter VX_bckE_req,
VX_wb_inter VX_writeback_inter,
VX_warp_ctl_inter VX_warp_ctl
);
VX_wb_inter VX_writeback_temp();
assign VX_writeback_inter.wb = VX_writeback_temp.wb;
assign VX_writeback_inter.rd = VX_writeback_temp.rd;
assign VX_writeback_inter.write_data = VX_writeback_temp.write_data;
assign VX_writeback_inter.wb_valid = VX_writeback_temp.wb_valid;
assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num;
assign VX_writeback_inter.wb_pc = VX_writeback_temp.wb_pc;
// assign VX_writeback_inter(VX_writeback_temp);
VX_mw_wb_inter VX_mw_wb();
wire no_slot_mem;
wire no_slot_exec;
VX_mem_req_inter VX_exe_mem_req();
VX_mem_req_inter VX_mem_req();
// LSU input + output
VX_lsu_req_inter VX_lsu_req();
VX_inst_mem_wb_inter VX_mem_wb();
// Exec unit input + output
VX_exec_unit_req_inter VX_exec_unit_req();
VX_inst_exec_wb_inter VX_inst_exec_wb();
// GPU unit input
VX_gpu_inst_req_inter VX_gpu_inst_req();
// CSR unit inputs
VX_csr_req_inter VX_csr_req();
VX_csr_wb_inter VX_csr_wb();
wire no_slot_csr;
wire stall_gpr_csr;
VX_gpr_stage VX_gpr_stage(
.clk (clk),
.reset (reset),
.schedule_delay (schedule_delay),
.VX_writeback_inter(VX_writeback_temp),
.VX_bckE_req (VX_bckE_req),
// New
.VX_exec_unit_req(VX_exec_unit_req),
.VX_lsu_req (VX_lsu_req),
.VX_gpu_inst_req (VX_gpu_inst_req),
.VX_csr_req (VX_csr_req),
.stall_gpr_csr (stall_gpr_csr),
// End new
.memory_delay (out_mem_delay),
.exec_delay (out_exec_delay),
.gpr_stage_delay (gpr_stage_delay)
);
VX_lsu load_store_unit(
.clk (clk),
.reset (reset),
.VX_lsu_req (VX_lsu_req),
.VX_mem_wb (VX_mem_wb),
.VX_dcache_rsp(VX_dcache_rsp),
.VX_dcache_req(VX_dcache_req),
.out_delay (out_mem_delay),
.no_slot_mem (no_slot_mem)
);
VX_execute_unit VX_execUnit(
.clk (clk),
.reset (reset),
.VX_exec_unit_req(VX_exec_unit_req),
.VX_inst_exec_wb (VX_inst_exec_wb),
.VX_jal_rsp (VX_jal_rsp),
.VX_branch_rsp (VX_branch_rsp),
.out_delay (out_exec_delay),
.no_slot_exec (no_slot_exec)
);
VX_gpgpu_inst VX_gpgpu_inst(
.VX_gpu_inst_req(VX_gpu_inst_req),
.VX_warp_ctl (VX_warp_ctl)
);
// VX_csr_wrapper VX_csr_wrapper(
// .VX_csr_req(VX_csr_req),
// .VX_csr_wb (VX_csr_wb)
// );
VX_csr_pipe #(.CORE_ID(CORE_ID)) VX_csr_pipe(
.clk (clk),
.reset (reset),
.no_slot_csr (no_slot_csr),
.VX_csr_req (VX_csr_req),
.VX_writeback(VX_writeback_temp),
.VX_csr_wb (VX_csr_wb),
.stall_gpr_csr(stall_gpr_csr)
);
VX_writeback VX_wb(
.clk (clk),
.reset (reset),
.VX_mem_wb (VX_mem_wb),
.VX_inst_exec_wb (VX_inst_exec_wb),
.VX_csr_wb (VX_csr_wb),
.VX_writeback_inter(VX_writeback_temp),
.no_slot_mem (no_slot_mem),
.no_slot_exec (no_slot_exec),
.no_slot_csr (no_slot_csr)
);
endmodule

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rtl/VX_cache/VX_bank.v
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`include "VX_cache_config.v"
`include "VX_define.v"
module VX_bank
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
parameter FUNC_ID = 0,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Forward SNP Queue
parameter FFSQ_SIZE = 8,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire clk,
input wire reset,
// Input Core Request
input wire delay_req,
input wire [NUMBER_REQUESTS-1:0] bank_valids,
input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr,
input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata,
input wire [4:0] bank_rd,
input wire [NUMBER_REQUESTS-1:0][1:0] bank_wb,
input wire [31:0] bank_pc,
input wire [`NW_M1:0] bank_warp_num,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_read,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_write,
output wire reqq_full,
// Output Core WB
input wire bank_wb_pop,
output wire bank_wb_valid,
output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] bank_wb_tid,
output wire [4:0] bank_wb_rd,
output wire [1:0] bank_wb_wb,
output wire [`NW_M1:0] bank_wb_warp_num,
output wire [`WORD_SIZE_RNG] bank_wb_data,
output wire [31:0] bank_wb_pc,
output wire [31:0] bank_wb_address,
// Dram Fill Requests
output wire dram_fill_req,
output wire[31:0] dram_fill_req_addr,
output wire dram_because_of_snp,
output wire dram_snp_full,
input wire dram_fill_req_queue_full,
// Dram Fill Response
input wire dram_fill_rsp,
input wire [31:0] dram_fill_addr,
input wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dram_fill_rsp_data,
output wire dram_fill_accept,
// Dram WB Requests
input wire dram_wb_queue_pop,
output wire dram_wb_req,
output wire[31:0] dram_wb_req_addr,
output wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dram_wb_req_data,
// Snp Request
input wire snp_req,
input wire[31:0] snp_req_addr,
output wire snrq_full,
output wire snp_fwd,
output wire[31:0] snp_fwd_addr,
input wire snp_fwd_pop
);
reg snoop_state = 0;
always @(posedge clk) begin
if (reset) begin
snoop_state <= 0;
end else begin
snoop_state <= (snoop_state | snp_req) && ((FUNC_ID == `LLFUNC_ID) || (FUNC_ID == `L3FUNC_ID));
end
end
wire snrq_pop;
wire snrq_empty;
wire snrq_valid_st0;
wire[31:0] snrq_addr_st0;
assign snrq_valid_st0 = !snrq_empty;
VX_generic_queue_ll #(.DATAW(32), .SIZE(SNRQ_SIZE)) snr_queue(
.clk (clk),
.reset (reset),
.push (snp_req),
.in_data (snp_req_addr),
.pop (snrq_pop),
.out_data(snrq_addr_st0),
.empty (snrq_empty),
.full (snrq_full)
);
wire dfpq_pop;
wire dfpq_empty;
wire dfpq_full;
wire[31:0] dfpq_addr_st0;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dfpq_filldata_st0;
assign dram_fill_accept = !dfpq_full;
VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*`WORD_SIZE)), .SIZE(DFPQ_SIZE)) dfp_queue(
.clk (clk),
.reset (reset),
.push (dram_fill_rsp),
.in_data ({dram_fill_addr, dram_fill_rsp_data}),
.pop (dfpq_pop),
.out_data({dfpq_addr_st0, dfpq_filldata_st0}),
.empty (dfpq_empty),
.full (dfpq_full)
);
wire reqq_pop;
wire reqq_push;
wire reqq_empty;
wire reqq_req_st0;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0;
wire [31:0] reqq_req_addr_st0;
wire [`WORD_SIZE_RNG] reqq_req_writeword_st0;
wire [4:0] reqq_req_rd_st0;
wire [1:0] reqq_req_wb_st0;
wire [`NW_M1:0] reqq_req_warp_num_st0;
wire [2:0] reqq_req_mem_read_st0;
wire [2:0] reqq_req_mem_write_st0;
wire [31:0] reqq_req_pc_st0;
assign reqq_push = !delay_req && (|bank_valids);
VX_cache_req_queue #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (NUMBER_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
)
req_queue
(
.clk (clk),
.reset (reset),
// Enqueue
.reqq_push (reqq_push),
.bank_valids (bank_valids),
.bank_addr (bank_addr),
.bank_writedata (bank_writedata),
.bank_rd (bank_rd),
.bank_pc (bank_pc),
.bank_wb (bank_wb),
.bank_warp_num (bank_warp_num),
.bank_mem_read (bank_mem_read),
.bank_mem_write (bank_mem_write),
// Dequeue
.reqq_pop (reqq_pop),
.reqq_req_st0 (reqq_req_st0),
.reqq_req_tid_st0 (reqq_req_tid_st0),
.reqq_req_addr_st0 (reqq_req_addr_st0),
.reqq_req_writedata_st0(reqq_req_writeword_st0),
.reqq_req_rd_st0 (reqq_req_rd_st0),
.reqq_req_wb_st0 (reqq_req_wb_st0),
.reqq_req_warp_num_st0 (reqq_req_warp_num_st0),
.reqq_req_mem_read_st0 (reqq_req_mem_read_st0),
.reqq_req_mem_write_st0(reqq_req_mem_write_st0),
.reqq_req_pc_st0 (reqq_req_pc_st0),
.reqq_empty (reqq_empty),
.reqq_full (reqq_full)
);
wire mrvq_pop;
wire mrvq_full;
wire mrvq_stop;
wire mrvq_valid_st0;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] mrvq_tid_st0;
wire [31:0] mrvq_addr_st0;
wire [`WORD_SIZE_RNG] mrvq_writeword_st0;
wire [4:0] mrvq_rd_st0;
wire [1:0] mrvq_wb_st0;
wire [31:0] miss_resrv_pc_st0;
wire [`NW_M1:0] mrvq_warp_num_st0;
wire [2:0] mrvq_mem_read_st0;
wire [2:0] mrvq_mem_write_st0;
wire miss_add;
wire[31:0] miss_add_addr;
wire[`WORD_SIZE_RNG] miss_add_data;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid;
wire[4:0] miss_add_rd;
wire[1:0] miss_add_wb;
wire[`NW_M1:0] miss_add_warp_num;
wire[2:0] miss_add_mem_read;
wire[2:0] miss_add_mem_write;
wire[31:0] miss_add_pc;
wire[31:0] addr_st2;
wire is_fill_st2;
VX_cache_miss_resrv #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (NUMBER_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
)
mrvq_queue
(
.clk (clk),
.reset (reset),
// Enqueue
.miss_add (miss_add), // Need to do all
.miss_add_addr (miss_add_addr),
.miss_add_data (miss_add_data),
.miss_add_tid (miss_add_tid),
.miss_add_rd (miss_add_rd),
.miss_add_wb (miss_add_wb),
.miss_add_warp_num (miss_add_warp_num),
.miss_add_mem_read (miss_add_mem_read),
.miss_add_mem_write (miss_add_mem_write),
.miss_add_pc (miss_add_pc),
.miss_resrv_full (mrvq_full),
.miss_resrv_stop (mrvq_stop),
// Broadcast
.is_fill_st1 (is_fill_st2),
.fill_addr_st1 (addr_st2),
// Dequeue
.miss_resrv_pop (mrvq_pop),
.miss_resrv_valid_st0 (mrvq_valid_st0),
.miss_resrv_addr_st0 (mrvq_addr_st0),
.miss_resrv_data_st0 (mrvq_writeword_st0),
.miss_resrv_tid_st0 (mrvq_tid_st0),
.miss_resrv_rd_st0 (mrvq_rd_st0),
.miss_resrv_wb_st0 (mrvq_wb_st0),
.miss_resrv_pc_st0 (miss_resrv_pc_st0),
.miss_resrv_warp_num_st0 (mrvq_warp_num_st0),
.miss_resrv_mem_read_st0 (mrvq_mem_read_st0),
.miss_resrv_mem_write_st0(mrvq_mem_write_st0)
);
wire stall_bank_pipe;
reg is_fill_in_pipe;
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire is_fill_st1 [STAGE_1_CYCLES-1:0];
wire going_to_write_st1[STAGE_1_CYCLES-1:0];
wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0];
reg[16:0] p_stage;
always @(*) begin
is_fill_in_pipe = 0;
for (p_stage = 0; p_stage < STAGE_1_CYCLES; p_stage=p_stage+1) begin
if (is_fill_st1[p_stage]) is_fill_in_pipe = 1;
end
if (is_fill_st2) is_fill_in_pipe = 1;
end
// assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2;
assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe;
assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe;
assign reqq_pop = !mrvq_stop && !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !is_fill_in_pipe;
assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe;
integer st1_cycle;
wire qual_is_fill_st0;
wire qual_valid_st0;
wire [31:0] qual_addr_st0;
wire [`WORD_SIZE_RNG] qual_writeword_st0;
wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] qual_writedata_st0;
wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0;
wire qual_going_to_write_st0;
wire qual_is_snp;
wire [31:0] qual_pc_st0;
wire [`WORD_SIZE_RNG] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0];
wire is_snp_st1 [STAGE_1_CYCLES-1:0];
wire [31:0] pc_st1 [STAGE_1_CYCLES-1:0];
assign qual_is_fill_st0 = dfpq_pop;
// always @(*) begin
// if (qual_is_fill_st0 && (FUNC_ID == 3)) begin
// $display("WHAT THE FUCK FUNC_ID: %x", FUNC_ID);
// end
// end
assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop;
assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 :
mrvq_pop ? mrvq_addr_st0 :
reqq_pop ? reqq_req_addr_st0 :
snrq_pop ? snrq_addr_st0 :
0;
assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 57;
assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0 , mrvq_wb_st0 , mrvq_warp_num_st0 , mrvq_mem_read_st0 , mrvq_mem_write_st0 , mrvq_tid_st0 } :
reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
0;
assign qual_going_to_write_st0 = dfpq_pop ? 1 :
(mrvq_pop && (mrvq_mem_write_st0 != `NO_MEM_WRITE)) ? 1 :
(reqq_pop && (reqq_req_mem_write_st0 != `NO_MEM_WRITE)) ? 1 :
(snrq_pop) ? 1 :
0;
assign qual_pc_st0 = (reqq_pop) ? reqq_req_pc_st0 :
(mrvq_pop) ? miss_resrv_pc_st0 :
(dfpq_pop) ? 32'hdeadbeef :
(snrq_pop) ? 32'hb00b0000 :
32'h0;
assign qual_is_snp = snrq_pop ? 1 : 0;
assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 :
reqq_pop ? reqq_req_writeword_st0 :
0;
VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({qual_is_snp , qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0, qual_pc_st0 }),
.out ({is_snp_st1[0], going_to_write_st1[0] , valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0] , pc_st1[0]})
);
genvar curr_stage;
generate
for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin
VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({is_snp_st1[curr_stage-1], going_to_write_st1[curr_stage-1], valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1], pc_st1[curr_stage-1]}),
.out ({is_snp_st1[curr_stage] , going_to_write_st1[curr_stage] , valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] , pc_st1[curr_stage]})
);
end
endgenerate
wire[`WORD_SIZE_RNG] readword_st1e;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st1e;
wire[`TAG_SELECT_SIZE_RNG] readtag_st1e;
wire miss_st1e;
wire dirty_st1e;
wire[31:0] pc_st1e;
wire [4:0] rd_st1e;
wire [1:0] wb_st1e;
wire [`NW_M1:0] warp_num_st1e;
wire [2:0] mem_read_st1e;
wire [2:0] mem_write_st1e;
wire [`vx_clog2(NUMBER_REQUESTS)-1:0] tid_st1e;
wire fill_saw_dirty_st1e;
wire is_snp_st1e;
assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1];
assign pc_st1e = pc_st1[STAGE_1_CYCLES-1];
assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
VX_tag_data_access #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (NUMBER_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
)
VX_tag_data_access
(
.clk (clk),
.reset (reset),
.stall (stall_bank_pipe),
.stall_bank_pipe(stall_bank_pipe),
// Initial Read
.readaddr_st10 (addr_st1[0]),
// Actual Read/Write
.valid_req_st1e(valid_st1[STAGE_1_CYCLES-1]),
.writefill_st1e(is_fill_st1[STAGE_1_CYCLES-1]),
.writeaddr_st1e(addr_st1[STAGE_1_CYCLES-1]),
.writeword_st1e(writeword_st1[STAGE_1_CYCLES-1]),
.writedata_st1e(writedata_st1[STAGE_1_CYCLES-1]),
.mem_write_st1e(mem_write_st1e),
.mem_read_st1e (mem_read_st1e),
.is_snp_st1e (is_snp_st1e),
// Read Data
.readword_st1e (readword_st1e),
.readdata_st1e (readdata_st1e),
.readtag_st1e (readtag_st1e),
.miss_st1e (miss_st1e),
.dirty_st1e (dirty_st1e),
.fill_saw_dirty_st1e(fill_saw_dirty_st1e)
);
wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1];
wire valid_st2;
wire[`WORD_SIZE_RNG] writeword_st2;
wire[`WORD_SIZE_RNG] readword_st2;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st2;
wire miss_st2;
wire dirty_st2;
wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
wire[`TAG_SELECT_SIZE_RNG] readtag_st2;
wire fill_saw_dirty_st2;
wire is_snp_st2;
wire [31:0] pc_st2;
VX_generic_register #(.N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_SIZE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32 + 2)) st_1e_2 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, pc_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 })
);
wire should_flush;
wire dwbq_push;
wire cwbq_full;
wire dwbq_full;
wire ffsq_full;
wire invalidate_fill;
// Enqueue to miss reserv if it's a valid miss
assign miss_add = valid_st2 && !is_snp_st2 && miss_st2 && !mrvq_full && !(should_flush && dwbq_push) && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
assign miss_add_pc = pc_st2;
assign miss_add_addr = addr_st2;
assign miss_add_data = writeword_st2;
assign {miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
// Enqueue to CWB Queue
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `LLFUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
wire [`WORD_SIZE_RNG] cwbq_data = readword_st2;
wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
wire [4:0] cwbq_rd = miss_add_rd;
wire [1:0] cwbq_wb = miss_add_wb;
wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num;
wire [31:0] cwbq_pc = pc_st2;
wire cwbq_empty;
assign bank_wb_valid = !cwbq_empty;
VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue(
.clk (clk),
.reset (reset),
.push (cwbq_push),
.in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}),
.pop (bank_wb_pop),
.out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data, bank_wb_pc, bank_wb_address}),
.empty (cwbq_empty),
.full (cwbq_full)
);
assign should_flush = snoop_state && valid_st2 && (miss_add_mem_write != `NO_MEM_WRITE) && !is_snp_st2 && !is_fill_st2;
// Enqueue to DWB Queue
assign dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2 || should_flush) && !dwbq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
wire[31:0] dwbq_req_addr;
wire dwbq_empty;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data;
if ((FUNC_ID == `LLFUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
assign dwbq_req_data = (should_flush && dwbq_push) ? writeword_st2 : readdata_st2;
assign dwbq_req_addr = (should_flush && dwbq_push) ? (addr_st2) : ({readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK);
end else begin
assign dwbq_req_data = readdata_st2;
assign dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK;
end
wire possible_fill = valid_st2 && miss_st2 && !dram_fill_req_queue_full && !is_snp_st2;
wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK;
VX_fill_invalidator #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (NUMBER_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
)
VX_fill_invalidator
(
.clk (clk),
.reset (reset),
.possible_fill (possible_fill),
.success_fill (is_fill_st2),
.fill_addr (fill_invalidator_addr),
.invalidate_fill (invalidate_fill)
);
// Enqueu in dram_fill_req
assign dram_fill_req = possible_fill && !invalidate_fill;
assign dram_because_of_snp = is_snp_st2 && valid_st2 && miss_st2;
assign dram_snp_full = snrq_full && snp_req;
assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK;
assign dram_wb_req = !dwbq_empty;
VX_generic_queue_ll #(.DATAW( 32 + (`BANK_LINE_SIZE_WORDS * `WORD_SIZE)), .SIZE(DWBQ_SIZE)) dwb_queue(
.clk (clk),
.reset (reset),
.push (dwbq_push),
.in_data ({dwbq_req_addr, dwbq_req_data}),
.pop (dram_wb_queue_pop),
.out_data({dram_wb_req_addr, dram_wb_req_data}),
.empty (dwbq_empty),
.full (dwbq_full)
);
wire snp_fwd_push;
wire ffsq_empty;
assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
assign snp_fwd = !ffsq_empty;
VX_generic_queue_ll #(.DATAW(32), .SIZE(FFSQ_SIZE)) ffs_queue(
.clk (clk),
.reset (reset),
.push (snp_fwd_push),
.in_data ({addr_st2}),
.pop (snp_fwd_pop),
.out_data({snp_fwd_addr}),
.empty (ffsq_empty),
.full (ffsq_full)
);
assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full);
endmodule : VX_bank

469
rtl/VX_cache/VX_cache.v
View File

@@ -1,469 +0,0 @@
`include "VX_cache_config.v"
module VX_cache
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 16,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
parameter FUNC_ID = 3,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Forward SNP Queue
parameter FFSQ_SIZE = 8,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Prefetcher
parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 0,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire clk,
input wire reset,
// Req Info
input wire [NUMBER_REQUESTS-1:0] core_req_valid,
input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_writedata,
input wire[NUMBER_REQUESTS-1:0][2:0] core_req_mem_read,
input wire[NUMBER_REQUESTS-1:0][2:0] core_req_mem_write,
// Req meta
input wire [4:0] core_req_rd,
input wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb,
input wire [`NW_M1:0] core_req_warp_num,
input wire [31:0] core_req_pc,
output wire delay_req,
// Core Writeback
input wire core_no_wb_slot,
output wire [NUMBER_REQUESTS-1:0] core_wb_valid,
output wire [4:0] core_wb_req_rd,
output wire [1:0] core_wb_req_wb,
output wire [`NW_M1:0] core_wb_warp_num,
output wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata,
output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_pc,
output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_address,
// Dram Fill Response
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [`IBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
output wire dram_fill_accept,
// Dram request
output wire dram_req,
output wire dram_req_write,
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire dram_req_because_of_wb,
input wire dram_req_delay,
output wire dram_snp_full,
// Snoop Req
input wire snp_req,
input wire[31:0] snp_req_addr,
output wire snp_req_delay,
// Snoop Forward
output wire snp_fwd,
output wire[31:0] snp_fwd_addr,
input wire snp_fwd_delay
);
wire [NUMBER_BANKS-1:0][NUMBER_REQUESTS-1:0] per_bank_valids;
wire [NUMBER_BANKS-1:0] per_bank_wb_pop;
wire [NUMBER_BANKS-1:0] per_bank_wb_valid;
wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid;
wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num;
wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data;
wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc;
wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address;
wire dfqq_full;
wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req;
wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
wire[NUMBER_BANKS-1:0] per_bank_dram_fill_accept;
wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop;
wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req;
wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp;
wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] per_bank_dram_wb_req_data;
wire[NUMBER_BANKS-1:0] per_bank_reqq_full;
wire[NUMBER_BANKS-1:0] per_bank_snrq_full;
wire[NUMBER_BANKS-1:0] per_bank_snp_fwd;
wire[NUMBER_BANKS-1:0][31:0] per_bank_snp_fwd_addr;
wire[NUMBER_BANKS-1:0] per_bank_snp_fwd_pop;
assign delay_req = (|per_bank_reqq_full);
assign snp_req_delay = (|per_bank_snrq_full);
// assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]];
assign dram_fill_accept = (|per_bank_dram_fill_accept);
VX_cache_dram_req_arb #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (NUMBER_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.PRFQ_SIZE (PRFQ_SIZE),
.PRFQ_STRIDE (PRFQ_STRIDE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
)
VX_cache_dram_req_arb
(
.clk (clk),
.reset (reset),
.dfqq_full (dfqq_full),
.per_bank_dram_fill_req (per_bank_dram_fill_req),
.per_bank_dram_fill_req_addr(per_bank_dram_fill_req_addr),
.per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop),
.per_bank_dram_wb_req (per_bank_dram_wb_req),
.per_bank_dram_because_of_snp(per_bank_dram_because_of_snp),
.per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr),
.per_bank_dram_wb_req_data (per_bank_dram_wb_req_data),
.dram_req (dram_req),
.dram_req_write (dram_req_write),
.dram_req_read (dram_req_read),
.dram_req_addr (dram_req_addr),
.dram_req_size (dram_req_size),
.dram_req_data (dram_req_data),
.dram_req_because_of_wb (dram_req_because_of_wb),
.dram_req_delay (dram_req_delay)
);
VX_cache_core_req_bank_sel #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (NUMBER_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
)
VX_cache_core_req_bank_sell
(
.core_req_valid (core_req_valid),
.core_req_addr (core_req_addr),
.per_bank_valids(per_bank_valids)
);
VX_cache_wb_sel_merge #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (NUMBER_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
)
VX_cache_core_wb_sel_merge
(
.per_bank_wb_valid (per_bank_wb_valid),
.per_bank_wb_tid (per_bank_wb_tid),
.per_bank_wb_rd (per_bank_wb_rd),
.per_bank_wb_pc (per_bank_wb_pc),
.per_bank_wb_wb (per_bank_wb_wb),
.per_bank_wb_warp_num(per_bank_wb_warp_num),
.per_bank_wb_data (per_bank_wb_data),
.per_bank_wb_pop (per_bank_wb_pop),
.per_bank_wb_address (per_bank_wb_address),
.core_no_wb_slot (core_no_wb_slot),
.core_wb_valid (core_wb_valid),
.core_wb_req_rd (core_wb_req_rd),
.core_wb_req_wb (core_wb_req_wb),
.core_wb_warp_num (core_wb_warp_num),
.core_wb_readdata (core_wb_readdata),
.core_wb_address (core_wb_address),
.core_wb_pc (core_wb_pc)
);
// Snoop Forward Logic
VX_snp_fwd_arb #(.NUMBER_BANKS(NUMBER_BANKS)) VX_snp_fwd_arb(
.per_bank_snp_fwd (per_bank_snp_fwd),
.per_bank_snp_fwd_addr(per_bank_snp_fwd_addr),
.per_bank_snp_fwd_pop (per_bank_snp_fwd_pop),
.snp_fwd (snp_fwd),
.snp_fwd_addr (snp_fwd_addr),
.snp_fwd_delay (snp_fwd_delay)
);
// Snoop Forward Logic
genvar curr_bank;
generate
for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin
wire [NUMBER_REQUESTS-1:0] curr_bank_valids;
wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_addr;
wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_writedata;
wire [4:0] curr_bank_rd;
wire [NUMBER_REQUESTS-1:0][1:0] curr_bank_wb;
wire [`NW_M1:0] curr_bank_warp_num;
wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_write;
wire [31:0] curr_bank_pc;
wire curr_bank_wb_pop;
wire curr_bank_wb_valid;
wire [`vx_clog2(NUMBER_REQUESTS)-1:0] curr_bank_wb_tid;
wire [31:0] curr_bank_wb_pc;
wire [4:0] curr_bank_wb_rd;
wire [1:0] curr_bank_wb_wb;
wire [`NW_M1:0] curr_bank_wb_warp_num;
wire [`WORD_SIZE_RNG] curr_bank_wb_data;
wire [31:0] curr_bank_wb_address;
wire curr_bank_dram_fill_rsp;
wire [31:0] curr_bank_dram_fill_rsp_addr;
wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data;
wire curr_bank_dram_fill_accept;
wire curr_bank_dfqq_full;
wire curr_bank_dram_fill_req;
wire curr_bank_dram_because_of_snp;
wire curr_bank_dram_snp_full;
wire[31:0] curr_bank_dram_fill_req_addr;
wire curr_bank_dram_wb_queue_pop;
wire curr_bank_dram_wb_req;
wire[31:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] curr_bank_dram_wb_req_data;
wire curr_bank_snp_req;
wire[31:0] curr_bank_snp_req_addr;
wire curr_bank_reqq_full;
wire curr_bank_snp_fwd;
wire[31:0] curr_bank_snp_fwd_addr;
wire curr_bank_snp_fwd_pop;
wire curr_bank_snrq_full;
// Core Req
assign curr_bank_valids = per_bank_valids[curr_bank];
assign curr_bank_addr = core_req_addr;
assign curr_bank_writedata = core_req_writedata;
assign curr_bank_rd = core_req_rd;
assign curr_bank_wb = core_req_wb;
assign curr_bank_pc = core_req_pc;
assign curr_bank_warp_num = core_req_warp_num;
assign curr_bank_mem_read = core_req_mem_read;
assign curr_bank_mem_write = core_req_mem_write;
assign per_bank_reqq_full[curr_bank] = curr_bank_reqq_full;
// Core WB
assign curr_bank_wb_pop = per_bank_wb_pop[curr_bank];
assign per_bank_wb_valid [curr_bank] = curr_bank_wb_valid;
assign per_bank_wb_tid [curr_bank] = curr_bank_wb_tid;
assign per_bank_wb_rd [curr_bank] = curr_bank_wb_rd;
assign per_bank_wb_wb [curr_bank] = curr_bank_wb_wb;
assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num;
assign per_bank_wb_data [curr_bank] = curr_bank_wb_data;
assign per_bank_wb_pc [curr_bank] = curr_bank_wb_pc;
assign per_bank_wb_address [curr_bank] = curr_bank_wb_address;
// Dram fill request
assign curr_bank_dfqq_full = dfqq_full;
assign per_bank_dram_fill_req[curr_bank] = curr_bank_dram_fill_req;
assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
// Dram fill response
assign curr_bank_dram_fill_rsp = (NUMBER_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank));
assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept;
// Dram writeback request
assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank];
assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req;
assign per_bank_dram_because_of_snp[curr_bank] = curr_bank_dram_because_of_snp;
assign per_bank_dram_wb_req_addr[curr_bank] = curr_bank_dram_wb_req_addr;
assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data;
// Snoop Request
assign curr_bank_snp_req = snp_req && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_snp_req_addr = snp_req_addr;
assign per_bank_snrq_full[curr_bank] = curr_bank_snrq_full;
// Snoop Fwd
assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[curr_bank];
assign per_bank_snp_fwd[curr_bank] = curr_bank_snp_fwd;
assign per_bank_snp_fwd_addr[curr_bank] = curr_bank_snp_fwd_addr;
VX_bank #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (NUMBER_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FFSQ_SIZE (FFSQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
)
bank
(
.clk (clk),
.reset (reset),
// Core req
.delay_req (delay_req),
.bank_valids (curr_bank_valids),
.bank_addr (curr_bank_addr),
.bank_writedata (curr_bank_writedata),
.bank_rd (curr_bank_rd),
.bank_wb (curr_bank_wb),
.bank_pc (curr_bank_pc),
.bank_warp_num (curr_bank_warp_num),
.bank_mem_read (curr_bank_mem_read),
.bank_mem_write (curr_bank_mem_write),
.reqq_full (curr_bank_reqq_full),
// Output core wb
.bank_wb_pop (curr_bank_wb_pop),
.bank_wb_valid (curr_bank_wb_valid),
.bank_wb_tid (curr_bank_wb_tid),
.bank_wb_rd (curr_bank_wb_rd),
.bank_wb_wb (curr_bank_wb_wb),
.bank_wb_warp_num (curr_bank_wb_warp_num),
.bank_wb_data (curr_bank_wb_data),
.bank_wb_pc (curr_bank_wb_pc),
.bank_wb_address (curr_bank_wb_address),
// Dram fill req
.dram_fill_req (curr_bank_dram_fill_req),
.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
.dram_fill_req_queue_full(curr_bank_dfqq_full),
// Dram fill rsp
.dram_fill_rsp (curr_bank_dram_fill_rsp),
.dram_fill_addr (curr_bank_dram_fill_rsp_addr),
.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
.dram_fill_accept (curr_bank_dram_fill_accept),
// Dram writeback
.dram_wb_queue_pop (curr_bank_dram_wb_queue_pop),
.dram_wb_req (curr_bank_dram_wb_req),
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
.dram_wb_req_data (curr_bank_dram_wb_req_data),
.dram_because_of_snp (curr_bank_dram_because_of_snp),
.dram_snp_full (curr_bank_dram_snp_full),
// Snoop Request
.snp_req (curr_bank_snp_req),
.snp_req_addr (curr_bank_snp_req_addr),
.snrq_full (curr_bank_snrq_full),
// Snoop Fwd
.snp_fwd (curr_bank_snp_fwd),
.snp_fwd_addr (curr_bank_snp_fwd_addr),
.snp_fwd_pop (curr_bank_snp_fwd_pop)
);
end
endgenerate
endmodule

130
rtl/VX_cache/VX_cache_config.v
View File

@@ -1,130 +0,0 @@
`ifndef VX_CACHE_CONFIG
`define VX_CACHE_CONFIG
`include "../VX_define.v"
// data tid rd wb warp_num read write
`define vx_clog2(value) ((value == 1) ? 1 : $clog2(value))
`define MRVQ_METADATA_SIZE (`WORD_SIZE + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3)
// 5 + 2 + 4 + 3 + 3 + 1
`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + `vx_clog2(NUMBER_REQUESTS))
// `define vx_clog2_h(value, x) (value == (1 << x)) ? (x)
// `define vx_clog2(value) (value == 0 ) ? 0 : \
// (value == 1 ) ? 1 : \
// `vx_clog2_h(value, 2 ) : \
// `vx_clog2_h(value, 3 ) : \
// `vx_clog2_h(value, 4 ) : \
// `vx_clog2_h(value, 5 ) : \
// `vx_clog2_h(value, 6 ) : \
// `vx_clog2_h(value, 7 ) : \
// `vx_clog2_h(value, 8 ) : \
// `vx_clog2_h(value, 9 ) : \
// `vx_clog2_h(value, 10) : \
// `vx_clog2_h(value, 11) : \
// `vx_clog2_h(value, 12) : \
// `vx_clog2_h(value, 13) : \
// `vx_clog2_h(value, 14) : \
// `vx_clog2_h(value, 15) : \
// `vx_clog2_h(value, 16) : \
// `vx_clog2_h(value, 17) : \
// `vx_clog2_h(value, 18) : \
// `vx_clog2_h(value, 19) : \
// `vx_clog2_h(value, 20) : \
// `vx_clog2_h(value, 21) : \
// `vx_clog2_h(value, 22) : \
// `vx_clog2_h(value, 23) : \
// `vx_clog2_h(value, 24) : \
// `vx_clog2_h(value, 25) : \
// `vx_clog2_h(value, 26) : \
// `vx_clog2_h(value, 27) : \
// `vx_clog2_h(value, 28) : \
// `vx_clog2_h(value, 29) : \
// `vx_clog2_h(value, 30) : \
// `vx_clog2_h(value, 31) : \
// 0
`define WORD_SIZE (8*WORD_SIZE_BYTES)
`define WORD_SIZE_RNG (`WORD_SIZE)-1:0
// 128
`define BANK_SIZE_BYTES CACHE_SIZE_BYTES/NUMBER_BANKS
// 8
`define BANK_LINE_COUNT (`BANK_SIZE_BYTES/BANK_LINE_SIZE_BYTES)
// 4
`define BANK_LINE_SIZE_WORDS (BANK_LINE_SIZE_BYTES / WORD_SIZE_BYTES)
// 3:0
`define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0
// Offset is fixed
`define OFFSET_ADDR_NUM_BITS 2
`define OFFSET_SIZE_END 1
`define OFFSET_ADDR_START 0
`define OFFSET_ADDR_END 1
`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START
`define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0
// 2
`define WORD_SELECT_NUM_BITS (`vx_clog2(`BANK_LINE_SIZE_WORDS))
// 2
`define WORD_SELECT_SIZE_END (`WORD_SELECT_NUM_BITS)
// 2
`define WORD_SELECT_ADDR_START (1+`OFFSET_ADDR_END)
// 3
`define WORD_SELECT_ADDR_END (`WORD_SELECT_SIZE_END+`OFFSET_ADDR_END)
// 3:2
`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START
`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:0
// 3
`define BANK_SELECT_NUM_BITS (`vx_clog2(NUMBER_BANKS))
// 3
`define BANK_SELECT_SIZE_END (`BANK_SELECT_NUM_BITS)
// 4
`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END)
// 6
`define BANK_SELECT_ADDR_END (`BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START-1)
// 6:4
`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START
// 2:0
`define BANK_SELECT_SIZE_RNG `BANK_SELECT_SIZE_END-1:0
// 3
`define LINE_SELECT_NUM_BITS (`vx_clog2(`BANK_LINE_COUNT))
// 3
`define LINE_SELECT_SIZE_END (`LINE_SELECT_NUM_BITS)
// 7
`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END)
// 9
`define LINE_SELECT_ADDR_END (`LINE_SELECT_SIZE_END+`LINE_SELECT_ADDR_START-1)
// 9:7
`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START
// 2:0
`define LINE_SELECT_SIZE_RNG `LINE_SELECT_SIZE_END-1:0
// 10
`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
// 31:10
`define TAG_SELECT_ADDR_RNG 31:`TAG_SELECT_ADDR_START
// 22
`define TAG_SELECT_NUM_BITS (32-`TAG_SELECT_ADDR_START)
// 22
`define TAG_SELECT_SIZE_END (`TAG_SELECT_NUM_BITS)
// 21:0
`define TAG_SELECT_SIZE_RNG `TAG_SELECT_SIZE_END-1:0
`define BASE_ADDR_MASK (~((1<<(`WORD_SELECT_ADDR_END+1))-1))
`endif

74
rtl/VX_cache/VX_cache_core_req_bank_sel.v
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@@ -1,74 +0,0 @@
`include "VX_cache_config.v"
module VX_cache_core_req_bank_sel
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
parameter FUNC_ID = 0,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire [NUMBER_REQUESTS-1:0] core_req_valid,
input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr,
output reg [NUMBER_BANKS-1:0][NUMBER_REQUESTS-1:0] per_bank_valids
);
wire[31:0] req_address;
generate
integer curr_req;
always @(*) begin
per_bank_valids = 0;
for (curr_req = 0; curr_req < NUMBER_REQUESTS; curr_req = curr_req + 1) begin
if (NUMBER_BANKS == 1) begin
// If there is only one bank, then only map requests to that bank
per_bank_valids[0][curr_req] = core_req_valid[curr_req];
end else begin
per_bank_valids[core_req_addr[curr_req][`BANK_SELECT_ADDR_RNG]][curr_req] = core_req_valid[curr_req];
end
end
end
endgenerate
endmodule

124
rtl/VX_cache/VX_cache_dfq_queue.v
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@@ -1,124 +0,0 @@
`include "VX_cache_config.v"
module VX_cache_dfq_queue
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire clk,
input wire reset,
input wire dfqq_push,
input wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req,
input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
input wire dfqq_pop,
output wire dfqq_req,
output wire[31:0] dfqq_req_addr,
output wire dfqq_empty,
output wire dfqq_full
);
wire[NUMBER_BANKS-1:0] out_per_bank_dram_fill_req;
wire[NUMBER_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr;
reg [NUMBER_BANKS-1:0] use_per_bank_dram_fill_req;
reg [NUMBER_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr;
wire[NUMBER_BANKS-1:0] qual_bank_dram_fill_req;
wire[NUMBER_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr;
wire[NUMBER_BANKS-1:0] updated_bank_dram_fill_req;
wire o_empty;
wire use_empty = !(|use_per_bank_dram_fill_req);
wire out_empty = !(|out_per_bank_dram_fill_req) || o_empty;
wire push_qual = dfqq_push && !dfqq_full;
wire pop_qual = dfqq_pop && use_empty && !out_empty;
VX_generic_queue_ll #(.DATAW(NUMBER_BANKS * (1+32)), .SIZE(DFQQ_SIZE)) dfqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),
.in_data ({per_bank_dram_fill_req, per_bank_dram_fill_req_addr}),
.pop (pop_qual),
.out_data({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}),
.empty (o_empty),
.full (dfqq_full)
);
assign qual_bank_dram_fill_req = use_empty ? (out_per_bank_dram_fill_req & {NUMBER_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req & {NUMBER_BANKS{!use_empty}});
assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr;
wire[`vx_clog2(NUMBER_BANKS)-1:0] qual_request_index;
wire qual_has_request;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank(
.valids(qual_bank_dram_fill_req),
.index (qual_request_index),
.found (qual_has_request)
);
assign dfqq_empty = !qual_has_request;
assign dfqq_req = qual_bank_dram_fill_req [qual_request_index];
assign dfqq_req_addr = qual_bank_dram_fill_req_addr[qual_request_index];
assign updated_bank_dram_fill_req = qual_bank_dram_fill_req & (~(1 << qual_request_index));
always @(posedge clk) begin
if (reset) begin
use_per_bank_dram_fill_req <= 0;
use_per_bank_dram_fill_req_addr <= 0;
end else begin
if (dfqq_pop && qual_has_request) begin
use_per_bank_dram_fill_req <= updated_bank_dram_fill_req;
use_per_bank_dram_fill_req_addr <= qual_bank_dram_fill_req_addr;
end
end
end
endmodule

151
rtl/VX_cache/VX_cache_dram_req_arb.v
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@@ -1,151 +0,0 @@
`include "VX_cache_config.v"
module VX_cache_dram_req_arb
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Prefetcher
parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 2,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire clk,
input wire reset,
// Fill Request
output wire dfqq_full,
input wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req,
input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
// DFQ Request
output wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop,
input wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req,
input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr,
input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] per_bank_dram_wb_req_data,
input wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp,
// real Dram request
output wire dram_req,
output wire dram_req_write,
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire dram_req_because_of_wb,
input wire dram_req_delay
);
wire pref_pop;
wire pref_valid;
wire[31:0] pref_addr;
wire dwb_valid;
wire dfqq_req;
assign pref_pop = !dwb_valid && !dfqq_req && !dram_req_delay && pref_valid;
VX_prefetcher #(
.PRFQ_SIZE (PRFQ_SIZE),
.PRFQ_STRIDE (PRFQ_STRIDE),
.BANK_LINE_SIZE_BYTES(BANK_LINE_SIZE_BYTES),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES)
)
prfqq
(
.clk (clk),
.reset (reset),
.dram_req (dram_req && dram_req_read),
.dram_req_addr(dram_req_addr),
.pref_pop (pref_pop),
.pref_valid (pref_valid),
.pref_addr (pref_addr)
);
wire[31:0] dfqq_req_addr;
wire dfqq_empty;
wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_delay; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req);
VX_cache_dfq_queue VX_cache_dfq_queue(
.clk (clk),
.reset (reset),
.dfqq_push (dfqq_push),
.per_bank_dram_fill_req (per_bank_dram_fill_req),
.per_bank_dram_fill_req_addr(per_bank_dram_fill_req_addr),
.dfqq_pop (dfqq_pop),
.dfqq_req (dfqq_req),
.dfqq_req_addr (dfqq_req_addr),
.dfqq_empty (dfqq_empty),
.dfqq_full (dfqq_full)
);
wire[`vx_clog2(NUMBER_BANKS)-1:0] dwb_bank;
// wire[NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp;
wire[NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_dwb(
.valids(use_wb_valid),
.index (dwb_bank),
.found (dwb_valid)
);
assign per_bank_dram_wb_queue_pop = dram_req_delay ? 0 : use_wb_valid & ((1 << dwb_bank));
assign dram_req = dwb_valid || dfqq_req || pref_pop;
assign dram_req_write = dwb_valid && dram_req;
assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req;
assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr)) & `BASE_ADDR_MASK;
assign dram_req_size = BANK_LINE_SIZE_BYTES;
assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0;
// assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0;
assign dram_req_because_of_wb = 0;
endmodule

176
rtl/VX_cache/VX_cache_miss_resrv.v
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@@ -1,176 +0,0 @@
`include "VX_cache_config.v"
module VX_cache_miss_resrv
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire clk,
input wire reset,
// Miss enqueue
input wire miss_add,
input wire[31:0] miss_add_addr,
input wire[`WORD_SIZE_RNG] miss_add_data,
input wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid,
input wire[4:0] miss_add_rd,
input wire[1:0] miss_add_wb,
input wire[`NW_M1:0] miss_add_warp_num,
input wire[2:0] miss_add_mem_read,
input wire[2:0] miss_add_mem_write,
input wire[31:0] miss_add_pc,
output wire miss_resrv_full,
output wire miss_resrv_stop,
// Broadcast Fill
input wire is_fill_st1,
input wire[31:0] fill_addr_st1,
// Miss dequeue
input wire miss_resrv_pop,
output wire miss_resrv_valid_st0,
output wire[31:0] miss_resrv_addr_st0,
output wire[`WORD_SIZE_RNG] miss_resrv_data_st0,
output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0,
output wire[4:0] miss_resrv_rd_st0,
output wire[1:0] miss_resrv_wb_st0,
output wire[`NW_M1:0] miss_resrv_warp_num_st0,
output wire[2:0] miss_resrv_mem_read_st0,
output wire[31:0] miss_resrv_pc_st0,
output wire[2:0] miss_resrv_mem_write_st0
);
// Size of metadata = 32 + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1)
reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[MRVQ_SIZE-1:0];
reg[MRVQ_SIZE-1:0][31:0] addr_table;
reg[MRVQ_SIZE-1:0][31:0] pc_table;
reg[MRVQ_SIZE-1:0] valid_table;
reg[MRVQ_SIZE-1:0] ready_table;
reg[`vx_clog2(MRVQ_SIZE)-1:0] head_ptr;
reg[`vx_clog2(MRVQ_SIZE)-1:0] tail_ptr;
reg[31:0] size;
// assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr;
assign miss_resrv_full = (MRVQ_SIZE != 2) && (size == MRVQ_SIZE );
assign miss_resrv_stop = (MRVQ_SIZE != 2) && (size > (MRVQ_SIZE-5));
wire enqueue_possible = !miss_resrv_full;
wire[`vx_clog2(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
reg[MRVQ_SIZE-1:0] make_ready;
genvar curr_e;
generate
for (curr_e = 0; curr_e < MRVQ_SIZE; curr_e=curr_e+1) begin
assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e]
&& addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START];
end
endgenerate
wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr];
wire[`vx_clog2(MRVQ_SIZE)-1:0] dequeue_index = head_ptr;
assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible;
assign miss_resrv_pc_st0 = pc_table[dequeue_index];
assign miss_resrv_addr_st0 = addr_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index];
wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2);
wire mrvq_pop = miss_resrv_pop && dequeue_possible;
wire update_ready = (|make_ready);
integer i;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < MRVQ_SIZE; i=i+1) metadata_table[i] <= 0;
valid_table <= 0;
ready_table <= 0;
addr_table <= 0;
pc_table <= 0;
size <= 0;
head_ptr <= 0;
tail_ptr <= 0;
end else begin
if (mrvq_push) begin
valid_table[enqueue_index] <= 1;
ready_table[enqueue_index] <= 0;
pc_table[enqueue_index] <= miss_add_pc;
addr_table[enqueue_index] <= miss_add_addr;
metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write};
tail_ptr <= tail_ptr + 1;
end
if (update_ready) begin
ready_table <= ready_table | make_ready;
end
if (mrvq_pop) begin
valid_table[dequeue_index] <= 0;
ready_table[dequeue_index] <= 0;
addr_table[dequeue_index] <= 0;
metadata_table[dequeue_index] <= 0;
pc_table[dequeue_index] <= 0;
head_ptr <= head_ptr + 1;
end
if (!(mrvq_push && mrvq_pop)) begin
if (mrvq_push) begin
size <= size + 1;
end
if (mrvq_pop) begin
size <= size - 1;
end
end
end
end
endmodule

208
rtl/VX_cache/VX_cache_req_queue.v
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@@ -1,208 +0,0 @@
`include "VX_cache_config.v"
module VX_cache_req_queue
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire clk,
input wire reset,
// Enqueue Data
input wire reqq_push,
input wire [NUMBER_REQUESTS-1:0] bank_valids,
input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr,
input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata,
input wire [4:0] bank_rd,
input wire [NUMBER_REQUESTS-1:0][1:0] bank_wb,
input wire [`NW_M1:0] bank_warp_num,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_read,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_write,
input wire [31:0] bank_pc,
// Dequeue Data
input wire reqq_pop,
output wire reqq_req_st0,
output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0,
output wire [31:0] reqq_req_addr_st0,
output wire [`WORD_SIZE_RNG] reqq_req_writedata_st0,
output wire [4:0] reqq_req_rd_st0,
output wire [1:0] reqq_req_wb_st0,
output wire [`NW_M1:0] reqq_req_warp_num_st0,
output wire [2:0] reqq_req_mem_read_st0,
output wire [2:0] reqq_req_mem_write_st0,
output wire [31:0] reqq_req_pc_st0,
// State Data
output wire reqq_empty,
output wire reqq_full
);
wire [NUMBER_REQUESTS-1:0] out_per_valids;
wire [NUMBER_REQUESTS-1:0][31:0] out_per_addr;
wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] out_per_writedata;
wire [4:0] out_per_rd;
wire [NUMBER_REQUESTS-1:0][1:0] out_per_wb;
wire [`NW_M1:0] out_per_warp_num;
wire [NUMBER_REQUESTS-1:0][2:0] out_per_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] out_per_mem_write;
wire [31:0] out_per_pc;
reg [NUMBER_REQUESTS-1:0] use_per_valids;
reg [NUMBER_REQUESTS-1:0][31:0] use_per_addr;
reg [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] use_per_writedata;
reg [4:0] use_per_rd;
reg [NUMBER_REQUESTS-1:0][1:0] use_per_wb;
reg [31:0] use_per_pc;
reg [`NW_M1:0] use_per_warp_num;
reg [NUMBER_REQUESTS-1:0][2:0] use_per_mem_read;
reg [NUMBER_REQUESTS-1:0][2:0] use_per_mem_write;
wire [NUMBER_REQUESTS-1:0] qual_valids;
wire [NUMBER_REQUESTS-1:0][31:0] qual_addr;
wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] qual_writedata;
wire [4:0] qual_rd;
wire [NUMBER_REQUESTS-1:0][1:0] qual_wb;
wire [`NW_M1:0] qual_warp_num;
wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_write;
wire [31:0] qual_pc;
reg [NUMBER_REQUESTS-1:0] updated_valids;
wire o_empty;
wire use_empty = !(|use_per_valids);
wire out_empty = !(|out_per_valids) || o_empty;
wire push_qual = reqq_push && !reqq_full;
wire pop_qual = !out_empty && use_empty;
VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUMBER_REQUESTS*2) + (`NW_M1+1) + (NUMBER_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),
.in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write , bank_pc}),
.pop (pop_qual),
.out_data({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write, out_per_pc}),
.empty (o_empty),
.full (reqq_full)
);
wire[NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUMBER_REQUESTS{~out_empty}};
assign qual_valids = use_per_valids;
assign qual_addr = use_per_addr;
assign qual_writedata = use_per_writedata;
assign qual_rd = use_per_rd;
assign qual_wb = use_per_wb;
assign qual_warp_num = use_per_warp_num;
assign qual_mem_read = use_per_mem_read;
assign qual_mem_write = use_per_mem_write;
assign qual_pc = use_per_pc;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] qual_request_index;
wire qual_has_request;
VX_generic_priority_encoder #(.N(NUMBER_REQUESTS)) VX_sel_bank(
.valids(qual_valids),
.index (qual_request_index),
.found (qual_has_request)
);
assign reqq_empty = !qual_has_request;
assign reqq_req_st0 = qual_has_request;
assign reqq_req_tid_st0 = qual_request_index;
assign reqq_req_addr_st0 = qual_addr [qual_request_index];
assign reqq_req_writedata_st0 = qual_writedata[qual_request_index];
assign reqq_req_rd_st0 = qual_rd;
assign reqq_req_wb_st0 = qual_wb[qual_request_index];
assign reqq_req_warp_num_st0 = qual_warp_num;
assign reqq_req_mem_read_st0 = qual_mem_read [qual_request_index];
assign reqq_req_mem_write_st0 = qual_mem_write[qual_request_index];
assign reqq_req_pc_st0 = qual_pc;
always @(*) begin
updated_valids = qual_valids;
if (qual_has_request) begin
updated_valids[qual_request_index] = 0;
end
end
always @(posedge clk) begin
if (reset) begin
use_per_valids <= 0;
use_per_addr <= 0;
use_per_writedata <= 0;
use_per_rd <= 0;
use_per_wb <= 0;
use_per_warp_num <= 0;
use_per_mem_read <= 0;
use_per_mem_write <= 0;
use_per_pc <= 0;
end else begin
if (pop_qual) begin
use_per_valids <= real_out_per_valids;
use_per_addr <= out_per_addr;
use_per_writedata <= out_per_writedata;
use_per_rd <= out_per_rd;
use_per_wb <= out_per_wb;
use_per_warp_num <= out_per_warp_num;
use_per_mem_read <= out_per_mem_read;
use_per_mem_write <= out_per_mem_write;
use_per_pc <= out_per_pc;
end else if (reqq_pop) begin
use_per_valids[qual_request_index] <= 0;
end
// else if (reqq_pop) begin
// use_per_valids[qual_request_index] <= updated_valids;
// end
end
end
endmodule

140
rtl/VX_cache/VX_cache_wb_sel_merge.v
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@@ -1,140 +0,0 @@
`include "VX_cache_config.v"
module VX_cache_wb_sel_merge
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
parameter FUNC_ID = 0,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
// Per Bank WB
input wire [NUMBER_BANKS-1:0] per_bank_wb_valid,
input wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid,
input wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd,
input wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb,
input wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num,
input wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data,
input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc,
input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address,
output wire [NUMBER_BANKS-1:0] per_bank_wb_pop,
// Core Writeback
input wire core_no_wb_slot,
output reg [NUMBER_REQUESTS-1:0] core_wb_valid,
output reg [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata,
output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_pc,
output wire [4:0] core_wb_req_rd,
output wire [1:0] core_wb_req_wb,
output wire [`NW_M1:0] core_wb_warp_num,
output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_address
);
reg [NUMBER_BANKS-1:0] per_bank_wb_pop_unqual;
assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUMBER_BANKS{~core_no_wb_slot}};
// wire[NUMBER_BANKS-1:0] bank_wants_wb;
// genvar curr_bank;
// generate
// for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin
// assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]);
// end
// endgenerate
wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index;
wire found_bank;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank(
.valids(per_bank_wb_valid),
.index (main_bank_index),
.found (found_bank)
);
assign core_wb_req_rd = per_bank_wb_rd [main_bank_index];
assign core_wb_req_wb = per_bank_wb_wb [main_bank_index];
assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index];
integer this_bank;
generate
always @(*) begin
core_wb_valid = 0;
core_wb_readdata = 0;
core_wb_pc = 0;
core_wb_address = 0;
for (this_bank = 0; this_bank < NUMBER_BANKS; this_bank = this_bank + 1) begin
if ((FUNC_ID == `LLFUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
if (found_bank && !core_wb_valid[per_bank_wb_tid[this_bank]] && per_bank_wb_valid[this_bank] && ((this_bank == main_bank_index) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin
core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];
core_wb_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
end else begin
per_bank_wb_pop_unqual[this_bank] = 0;
end
end else begin
if (((this_bank == main_bank_index) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index])) && found_bank && !core_wb_valid[per_bank_wb_tid[this_bank]] && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin
core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];
core_wb_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
end else begin
per_bank_wb_pop_unqual[this_bank] = 0;
end
end
end
end
endgenerate
endmodule

85
rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v
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@@ -1,85 +0,0 @@
`include "VX_cache_config.v"
module VX_dcache_llv_resp_bank_sel
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
output reg [NUMBER_BANKS-1:0] per_bank_llvq_pop,
input wire[NUMBER_BANKS-1:0] per_bank_llvq_valid,
input wire[NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr,
input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data,
input wire[NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid,
input wire llvq_pop,
output reg[NUMBER_REQUESTS-1:0] llvq_valid,
output reg[NUMBER_REQUESTS-1:0][31:0] llvq_res_addr,
output reg[NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data
);
wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index;
wire found_bank;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank(
.valids(per_bank_llvq_valid),
.index (main_bank_index),
.found (found_bank)
);
always @(*) begin
llvq_valid = 0;
llvq_res_addr = 0;
llvq_res_data = 0;
per_bank_llvq_pop = 0;
if (found_bank && llvq_pop) begin
llvq_valid [per_bank_llvq_res_tid[main_bank_index]] = 1'b1;
llvq_res_addr[per_bank_llvq_res_tid[main_bank_index]] = per_bank_llvq_res_addr[main_bank_index];
llvq_res_data[per_bank_llvq_res_tid[main_bank_index]] = per_bank_llvq_res_data[main_bank_index];
per_bank_llvq_pop[main_bank_index] = 1'b1;
end
end
endmodule

172
rtl/VX_cache/VX_fill_invalidator.v
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@@ -1,172 +0,0 @@
`include "VX_cache_config.v"
module VX_fill_invalidator
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire clk,
input wire reset,
input wire possible_fill,
input wire success_fill,
input wire[31:0] fill_addr,
output reg invalidate_fill
);
if (FILL_INVALIDAOR_SIZE == 0) begin
assign invalidate_fill = 0;
end else begin
reg[FILL_INVALIDAOR_SIZE-1:0] fills_active;
reg[FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address;
reg[FILL_INVALIDAOR_SIZE-1:0] matched_fill;
wire matched;
integer fi;
always @(*) begin
for (fi = 0; fi < FILL_INVALIDAOR_SIZE; fi+=1) begin
matched_fill[fi] = fills_active[fi] && (fills_address[fi][31:`LINE_SELECT_ADDR_START] == fill_addr[31:`LINE_SELECT_ADDR_START]);
end
end
assign matched = (|(matched_fill));
wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
wire enqueue_found;
VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank(
.valids(~fills_active),
.index (enqueue_index),
.found (enqueue_found)
);
assign invalidate_fill = possible_fill && matched;
always @(posedge clk) begin
if (reset) begin
fills_active <= 0;
fills_address <= 0;
end else begin
if (possible_fill && !matched && enqueue_found) begin
fills_active [enqueue_index] <= 1;
fills_address[enqueue_index] <= fill_addr;
end else if (success_fill && matched) begin
fills_active <= fills_active & (~matched_fill);
end
end
end
// reg success_found;
// reg[(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] success_index;
// integer curr_fill;
// always @(*) begin
// invalidate_fill = 0;
// success_found = 0;
// success_index = 0;
// for (curr_fill = 0; curr_fill < FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
// if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
// if (possible_fill && fills_active[curr_fill]) begin
// invalidate_fill = 1;
// end
// if (success_fill) begin
// success_found = 1;
// success_index = curr_fill;
// end
// end
// end
// end
// wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
// wire enqueue_found;
// VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank(
// .valids(~fills_active),
// .index (enqueue_index),
// .found (enqueue_found)
// );
// always @(posedge clk) begin
// if (reset) begin
// fills_active <= 0;
// fills_address <= 0;
// end else begin
// if (possible_fill && !invalidate_fill) begin
// fills_active[enqueue_index] <= 1;
// fills_address[enqueue_index] <= fill_addr;
// end
// if (success_found) begin
// fills_active[success_index] <= 0;
// end
// end
// end
end
endmodule

122
rtl/VX_cache/VX_mrv_queue.v
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@@ -1,122 +0,0 @@
module VX_mrv_queue
#(
parameter DATAW = 4,
parameter SIZE = 277
)
(
input wire clk,
input wire reset,
input wire push,
input wire[DATAW-1:0] in_data,
input wire pop,
output wire[DATAW-1:0] out_data,
output wire empty,
output wire full
);
if (SIZE == 0) begin
assign empty = 1;
assign out_data = 0;
assign full = 0;
end else begin
reg[DATAW-1:0] data[SIZE-1:0], curr_r, head_r;
reg[$clog2(SIZE+1)-1:0] size_r;
reg[$clog2(SIZE)-1:0] wr_ctr_r;
reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r;
reg empty_r, full_r, bypass_r;
wire reading, writing;
assign reading = pop && !empty;
assign writing = push && !full;
if (SIZE == 1) begin
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= 1;
end else if (reading && !writing) begin
size_r <= 0;
end
if (writing) begin
head_r <= in_data;
end
end
end
assign out_data = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0) && !pop;
end else begin
always @(posedge clk) begin
if (reset) begin
wr_ctr_r <= 0;
end else begin
if (writing)
wr_ctr_r <= wr_ctr_r + 1;
end
end
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
empty_r <= 1;
full_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= size_r + 1;
empty_r <= 0;
if (size_r == SIZE-1)
full_r <= 1;
end else if (reading && !writing) begin
size_r <= size_r - 1;
if (size_r == 1)
empty_r <= 1;
full_r <= 0;
end
end
end
always @(posedge clk) begin
if (writing) begin
data[wr_ctr_r] <= in_data;
end
end
always @(posedge clk) begin
if (reset) begin
rd_ptr_r <= 0;
rd_next_ptr_r <= 1;
bypass_r <= 0;
end else begin
if (reading) begin
if (SIZE == 2) begin
rd_ptr_r <= rd_next_ptr_r;
rd_next_ptr_r <= ~rd_next_ptr_r;
end else if (SIZE > 2) begin
rd_ptr_r <= rd_next_ptr_r;
rd_next_ptr_r <= rd_ptr_r + 2;
end
end
bypass_r <= writing && (empty_r || (1 == size_r) && reading);
curr_r <= in_data;
head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r];
end
end
assign out_data = bypass_r ? curr_r : head_r;
assign empty = empty_r;
assign full = full_r;
end
end
endmodule

77
rtl/VX_cache/VX_prefetcher.v
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@@ -1,77 +0,0 @@
`include "VX_cache_config.v"
module VX_prefetcher
#(
parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 2,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4
)
(
input wire clk,
input wire reset,
input wire dram_req,
input wire[31:0] dram_req_addr,
input wire pref_pop,
output wire pref_valid,
output wire[31:0] pref_addr
);
reg[`vx_clog2(PRFQ_STRIDE):0] use_valid;
reg[31:0] use_addr;
wire current_valid;
wire[31:0] current_addr;
wire current_full;
wire current_empty;
assign current_valid = ~current_empty;
wire update_use = ((use_valid == 0) || ((use_valid-1) == 0)) && current_valid;
VX_generic_queue_ll #(.DATAW(32), .SIZE(PRFQ_SIZE)) pfq_queue(
.clk (clk),
.reset (reset),
.push (dram_req && !current_full && !pref_pop),
.in_data (dram_req_addr & `BASE_ADDR_MASK),
.pop (update_use),
.out_data(current_addr),
.empty (current_empty),
.full (current_full)
);
assign pref_valid = use_valid != 0;
assign pref_addr = use_addr;
always @(posedge clk) begin
if (reset) begin
use_valid <= 0;
use_addr <= 0;
end else begin
if (update_use) begin
use_valid <= PRFQ_STRIDE;
use_addr <= current_addr + BANK_LINE_SIZE_BYTES;
end else if (pref_valid && pref_pop) begin
use_valid <= use_valid - 1;
use_addr <= use_addr + BANK_LINE_SIZE_BYTES;
end
end
end
endmodule

40
rtl/VX_cache/VX_snp_fwd_arb.v
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@@ -1,40 +0,0 @@
`include "VX_cache_config.v"
module VX_snp_fwd_arb
#(
parameter NUMBER_BANKS = 8
)
(
input wire[NUMBER_BANKS-1:0] per_bank_snp_fwd,
input wire[NUMBER_BANKS-1:0][31:0] per_bank_snp_fwd_addr,
output reg[NUMBER_BANKS-1:0] per_bank_snp_fwd_pop,
output wire snp_fwd,
output wire[31:0] snp_fwd_addr,
input wire snp_fwd_delay
);
wire[NUMBER_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUMBER_BANKS{!snp_fwd_delay}};
wire[`vx_clog2(NUMBER_BANKS)-1:0] fsq_bank;
wire fsq_valid;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_ffsq(
.valids(qual_per_bank_snp_fwd),
.index (fsq_bank),
.found (fsq_valid)
);
assign snp_fwd = fsq_valid;
assign snp_fwd_addr = per_bank_snp_fwd_addr[fsq_bank];
always @(*) begin
per_bank_snp_fwd_pop = 0;
if (fsq_valid) begin
per_bank_snp_fwd_pop[fsq_bank] = 1;
end
end
endmodule

295
rtl/VX_cache/VX_tag_data_access.v
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@@ -1,295 +0,0 @@
`include "VX_cache_config.v"
module VX_tag_data_access
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
parameter FUNC_ID = 0,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire clk,
input wire reset,
input wire stall,
input wire is_snp_st1e,
input wire stall_bank_pipe,
// Initial Reading
input wire[31:0] readaddr_st10,
// Write/Read Logic
input wire valid_req_st1e,
input wire writefill_st1e,
input wire[31:0] writeaddr_st1e,
input wire[`WORD_SIZE_RNG] writeword_st1e,
input wire[`DBANK_LINE_SIZE_RNG][31:0] writedata_st1e,
input wire[2:0] mem_write_st1e,
input wire[2:0] mem_read_st1e,
output wire[`WORD_SIZE_RNG] readword_st1e,
output wire[`DBANK_LINE_SIZE_RNG][31:0] readdata_st1e,
output wire[`TAG_SELECT_SIZE_RNG] readtag_st1e,
output wire miss_st1e,
output wire dirty_st1e,
output wire fill_saw_dirty_st1e
);
reg[`DBANK_LINE_SIZE_RNG][31:0] readdata_st[STAGE_1_CYCLES-1:0];
reg read_valid_st1c[STAGE_1_CYCLES-1:0];
reg read_dirty_st1c[STAGE_1_CYCLES-1:0];
reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-1:0];
reg[`DBANK_LINE_SIZE_RNG][31:0] read_data_st1c [STAGE_1_CYCLES-1:0];
wire qual_read_valid_st1;
wire qual_read_dirty_st1;
wire[`TAG_SELECT_SIZE_RNG] qual_read_tag_st1;
wire[`DBANK_LINE_SIZE_RNG][31:0] qual_read_data_st1;
wire use_read_valid_st1e;
wire use_read_dirty_st1e;
wire[`TAG_SELECT_SIZE_RNG] use_read_tag_st1e;
wire[`DBANK_LINE_SIZE_RNG][31:0] use_read_data_st1e;
wire[`DBANK_LINE_SIZE_RNG][3:0] use_write_enable;
wire[`DBANK_LINE_SIZE_RNG][31:0] use_write_data;
wire sw, sb, sh;
wire real_writefill = writefill_st1e && ((valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)));
wire fill_sent;
wire invalidate_line;
VX_tag_data_structure #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (NUMBER_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
)
VX_tag_data_structure
(
.clk (clk),
.reset (reset),
.stall_bank_pipe(stall_bank_pipe),
.read_addr (readaddr_st10),
.read_valid (qual_read_valid_st1),
.read_dirty (qual_read_dirty_st1),
.read_tag (qual_read_tag_st1),
.read_data (qual_read_data_st1),
.invalidate (invalidate_line),
.write_enable(use_write_enable),
.write_fill (real_writefill),
.write_addr (writeaddr_st1e),
.write_data (use_write_data),
.fill_sent (fill_sent)
);
// VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) )) s0_1_c0 (
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) ), .Valid(0)) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(0),
.in ({qual_read_valid_st1, qual_read_dirty_st1, qual_read_tag_st1, qual_read_data_st1}),
.out ({read_valid_st1c[0] , read_dirty_st1c[0] , read_tag_st1c[0] , read_data_st1c[0]})
);
genvar curr_stage;
generate
for (curr_stage = 1; curr_stage < STAGE_1_CYCLES-1; curr_stage = curr_stage + 1) begin
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) )) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(0),
.in ({read_valid_st1c[curr_stage-1] , read_dirty_st1c[curr_stage-1] , read_tag_st1c[curr_stage-1] , read_data_st1c[curr_stage-1]}),
.out ({read_valid_st1c[curr_stage] , read_dirty_st1c[curr_stage] , read_tag_st1c[curr_stage] , read_data_st1c[curr_stage] })
);
end
endgenerate
assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || (FUNC_ID == `SFUNC_ID); // If shared memory, always valid
assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && (FUNC_ID != `SFUNC_ID); // Dirty only applies in Dcache
assign use_read_tag_st1e = (FUNC_ID == `SFUNC_ID) ? writeaddr_st1e[`TAG_SELECT_ADDR_RNG] : read_tag_st1c [STAGE_1_CYCLES-1]; // Tag is always the same in SM
genvar curr_w;
for (curr_w = 0; curr_w < `DBANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-1][curr_w][31:0];
// assign use_read_data_st1e = read_data_st1c [STAGE_1_CYCLES-1];
/////////////////////// LOAD LOGIC ///////////////////
wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG];
wire[`WORD_SELECT_SIZE_RNG] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG];
wire lw = valid_req_st1e && (mem_read_st1e == `LW_MEM_READ);
wire lb = valid_req_st1e && (mem_read_st1e == `LB_MEM_READ);
wire lh = valid_req_st1e && (mem_read_st1e == `LH_MEM_READ);
wire lhu = valid_req_st1e && (mem_read_st1e == `LHU_MEM_READ);
wire lbu = valid_req_st1e && (mem_read_st1e == `LBU_MEM_READ);
wire b0 = (byte_select == 0);
wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-1][0][31:0];
wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-1][1][31:0];
wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-1][2][31:0];
wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-1][3][31:0];
wire[31:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-1][block_offset][31:0];
wire[31:0] data_unQual = (b0 || lw) ? (data_unmod) :
b1 ? (data_unmod >> 8) :
b2 ? (data_unmod >> 16) :
(data_unmod >> 24);
wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF);
wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF);
wire[31:0] lbu_data = (data_unQual & 32'hFF);
wire[31:0] lhu_data = (data_unQual & 32'hFFFF);
wire[31:0] lw_data = (data_unQual);
wire[31:0] sw_data = writeword_st1e[31:0];
wire[31:0] sb_data = b1 ? {{16{1'b0}}, writeword_st1e[7:0], { 8{1'b0}}} :
b2 ? {{ 8{1'b0}}, writeword_st1e[7:0], {16{1'b0}}} :
b3 ? {{ 0{1'b0}}, writeword_st1e[7:0], {24{1'b0}}} :
writeword_st1e[31:0];
wire[31:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e[31:0];
wire[31:0] use_write_dat = sb ? sb_data :
sh ? sh_data :
sw_data;
wire[31:0] data_Qual = lb ? lb_data :
lh ? lh_data :
lhu ? lhu_data :
lbu ? lbu_data :
lw_data;
/////////////////////// STORE LOGIC ///////////////////
assign sw = valid_req_st1e && (mem_write_st1e == `SW_MEM_WRITE);
assign sb = valid_req_st1e && (mem_write_st1e == `SB_MEM_WRITE);
assign sh = valid_req_st1e && (mem_write_st1e == `SH_MEM_WRITE);
wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e && !is_snp_st1e;
wire force_write = real_writefill;
wire[`DBANK_LINE_SIZE_RNG][3:0] we;
wire[`DBANK_LINE_SIZE_RNG][31:0] data_write;
genvar g;
generate
for (g = 0; g < `DBANK_LINE_SIZE_WORDS; g = g + 1) begin : write_enables
wire normal_write = (block_offset == g[`WORD_SELECT_SIZE_RNG]) && should_write && !real_writefill;
assign we[g] = (force_write) ? 4'b1111 :
(should_write && !real_writefill && (FUNC_ID == `LLFUNC_ID)) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :
4'b0000;
if (!(FUNC_ID == `LLFUNC_ID)) assign data_write[g] = force_write ? writedata_st1e[g] : use_write_dat;
end
if ((FUNC_ID == `LLFUNC_ID)) begin
assign data_write = force_write ? writedata_st1e : writeword_st1e;
end
endgenerate
assign use_write_enable = (writefill_st1e && !real_writefill) ? 0 : we;
assign use_write_data = data_write;
///////////////////////
if (FUNC_ID == `LLFUNC_ID) begin
assign readword_st1e = read_data_st1c[STAGE_1_CYCLES-1];
end else begin
assign readword_st1e = data_Qual;
end
wire[`TAG_SELECT_ADDR_RNG] writeaddr_tag = writeaddr_st1e[`TAG_SELECT_ADDR_RNG];
wire tags_mismatch = writeaddr_tag != use_read_tag_st1e;
wire tags_match = writeaddr_tag == use_read_tag_st1e;
wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && use_read_dirty_st1e;
wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e;
wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && tags_mismatch;
assign miss_st1e = snoop_hit || req_invalid || req_miss;
assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e;
assign readdata_st1e = use_read_data_st1e;
assign readtag_st1e = use_read_tag_st1e;
assign fill_sent = miss_st1e;
assign fill_saw_dirty_st1e = real_writefill && dirty_st1e;
assign invalidate_line = snoop_hit;
endmodule

122
rtl/VX_cache/VX_tag_data_structure.v
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@@ -1,122 +0,0 @@
`include "VX_cache_config.v"
module VX_tag_data_structure
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
parameter FUNC_ID = 0,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire clk,
input wire reset,
input wire stall_bank_pipe,
input wire[31:0] read_addr,
output wire read_valid,
output wire read_dirty,
output wire[`TAG_SELECT_SIZE_RNG] read_tag,
output wire[`DBANK_LINE_SIZE_RNG][31:0] read_data,
input wire invalidate,
input wire[`DBANK_LINE_SIZE_RNG][3:0] write_enable,
input wire write_fill,
input wire[31:0] write_addr,
input wire[`DBANK_LINE_SIZE_RNG][31:0] write_data,
input wire fill_sent
);
reg[`DBANK_LINE_SIZE_RNG][3:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg[`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0];
reg valid[`BANK_LINE_COUNT-1:0];
reg dirty[`BANK_LINE_COUNT-1:0];
wire[`TAG_SELECT_ADDR_RNG] curr_tag = write_addr[`TAG_SELECT_ADDR_RNG];
wire[`LINE_SELECT_ADDR_RNG] curr_inx = write_addr[`LINE_SELECT_ADDR_RNG];
assign read_valid = valid[read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_dirty = dirty[read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_tag = tag [read_addr[`LINE_SELECT_ADDR_RNG]];
assign read_data = data [read_addr[`LINE_SELECT_ADDR_RNG]];
wire going_to_write = (|write_enable);
integer f;
integer l;
always @(posedge clk) begin
if (reset) begin
for (l = 0; l < `BANK_LINE_COUNT; l=l+1) begin
valid[l] <= 0;
// tag [l] <= 0;
dirty[l] <= 0;
// data [l] <= 0;
end
end else if (!stall_bank_pipe) begin
if (going_to_write) begin
valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1;
tag [write_addr[`LINE_SELECT_ADDR_RNG]] <= write_addr[`TAG_SELECT_ADDR_RNG];
if (write_fill) begin
dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
end else begin
dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 1;
end
end else if (fill_sent) begin
dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
// valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
end
if (invalidate) begin
valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
end
for (f = 0; f < `DBANK_LINE_SIZE_WORDS; f = f + 1) begin
if (write_enable[f][0]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][0] <= write_data[f][7 :0 ];
if (write_enable[f][1]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][1] <= write_data[f][15:8 ];
if (write_enable[f][2]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][2] <= write_data[f][23:16];
if (write_enable[f][3]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][3] <= write_data[f][31:24];
end
end
end
endmodule

72
rtl/VX_cache/quartus/Makefile
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@@ -1,72 +0,0 @@
PROJECT = VX_cache
TOP_LEVEL_ENTITY = VX_cache
SRC_FILE = ../VX_cache.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
QUARTUS_ROOT ?= /tools/reconfig/intel/18.0
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
# Executable Configuration
SYN_ARGS = --parallel --read_settings_files=on
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
ASM_ARGS =
STA_ARGS = --do_report_timing
# Build targets
all: $(PROJECT).sta.rpt
syn: $(PROJECT).syn.rpt
fit: $(PROJECT).fit.rpt
asm: $(PROJECT).asm.rpt
sta: $(PROJECT).sta.rpt
smart: smart.log
# Target implementations
STAMP = echo done >
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
quartus_sta $(PROJECT) $(STA_ARGS)
smart.log: $(PROJECT_FILES)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization
$(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../;../../"
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean:
rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

1
rtl/VX_cache/quartus/project.sdc
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@@ -1 +0,0 @@
create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

41
rtl/VX_cache/quartus/project.tcl
View File

@@ -1,41 +0,0 @@
load_package flow
package require cmdline
set options { \
{ "project.arg" "" "Project name" } \
{ "family.arg" "" "Device family name" } \
{ "device.arg" "" "Device name" } \
{ "top.arg" "" "Top level module" } \
{ "sdc.arg" "" "Timing Design Constraints file" } \
{ "src.arg" "" "Verilog source file" } \
{ "inc.arg" "." "Include path" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name VERILOG_FILE $opts(src)
set_global_assignment -name SEARCH_PATH $opts(inc)
set_global_assignment -name SDC_FILE $opts(sdc)
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
proc make_all_pins_virtual {} {
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
}
make_all_pins_virtual
project_close

22
rtl/VX_countones.v
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@@ -1,22 +0,0 @@
module VX_countones
#(
parameter N = 10
)
(
input wire[N-1:0] valids,
output reg[$clog2(N):0] count
);
integer i;
always @(*) begin
count = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
count = count + 1;
end
end
end
endmodule

89
rtl/VX_csr_data.v
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@@ -1,89 +0,0 @@
`include "../VX_define.v"
module VX_csr_data (
input wire clk, // Clock
input wire reset,
input wire[11:0] in_read_csr_address,
input wire in_write_valid,
input wire[31:0] in_write_csr_data,
input wire[11:0] in_write_csr_address,
output wire[31:0] out_read_csr_data,
// For instruction retire counting
input wire in_writeback_valid
);
/* verilator lint_off WIDTH */
// wire[`NT_M1:0][31:0] thread_ids;
// wire[`NT_M1:0][31:0] warp_ids;
// genvar cur_t;
// for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin
// assign thread_ids[cur_t] = cur_t;
// end
// genvar cur_tw;
// for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin
// assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, in_read_warp_num};
// end
reg[11:0] csr[1023:0];
reg[63:0] cycle;
reg[63:0] instret;
wire read_cycle;
wire read_cycleh;
wire read_instret;
wire read_instreth;
assign read_cycle = in_read_csr_address == 12'hC00;
assign read_cycleh = in_read_csr_address == 12'hC80;
assign read_instret = in_read_csr_address == 12'hC02;
assign read_instreth = in_read_csr_address == 12'hC82;
// wire thread_select = in_read_csr_address == 12'h20;
// wire warp_select = in_read_csr_address == 12'h21;
// assign out_read_csr_data = thread_select ? thread_ids :
// warp_select ? warp_ids :
// 0;
integer curr_e;
always @(posedge clk or posedge reset) begin
if (reset) begin
for (curr_e = 0; curr_e < 1024; curr_e=curr_e+1) begin
`ifdef VERILATOR
// - Verilator does not support delayed assignment in loops.
csr[curr_e] = 0;
`else
csr[curr_e] <= 0;
`endif
end
cycle <= 0;
instret <= 0;
end else begin
cycle <= cycle + 1;
if (in_write_valid) begin
csr[in_write_csr_address] <= in_write_csr_data[11:0];
end
if (in_writeback_valid) begin
instret <= instret + 1;
end
end
end
assign out_read_csr_data = read_cycle ? cycle[31:0] :
read_cycleh ? cycle[63:32] :
read_instret ? instret[31:0] :
read_instreth ? instret[63:32] :
{{20{1'b0}}, csr[in_read_csr_address]};
/* verilator lint_on WIDTH */
endmodule : VX_csr_data

84
rtl/VX_csr_handler.v
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@@ -1,84 +0,0 @@
module VX_csr_handler (
input wire clk,
input wire[11:0] in_decode_csr_address, // done
VX_csr_write_request_inter VX_csr_w_req,
input wire in_wb_valid,
output wire[31:0] out_decode_csr_data // done
);
wire in_mem_is_csr;
wire[11:0] in_mem_csr_address;
/* verilator lint_off UNUSED */
wire[31:0] in_mem_csr_result;
/* verilator lint_on UNUSED */
assign in_mem_is_csr = VX_csr_w_req.is_csr;
assign in_mem_csr_address = VX_csr_w_req.csr_address;
assign in_mem_csr_result = VX_csr_w_req.csr_result;
reg[1024:0][11:0] csr;
reg[63:0] cycle;
reg[63:0] instret;
reg[11:0] decode_csr_address;
wire read_cycle;
wire read_cycleh;
wire read_instret;
wire read_instreth;
initial begin
cycle = 0;
instret = 0;
decode_csr_address = 0;
end
always @(posedge clk) begin
cycle <= cycle + 1;
decode_csr_address <= in_decode_csr_address;
if (in_wb_valid) begin
instret <= instret + 1;
end
end
reg[11:0] data_read;
always @(posedge clk) begin
if(in_mem_is_csr) begin
csr[in_mem_csr_address] <= in_mem_csr_result[11:0];
end
end
assign data_read = csr[decode_csr_address];
assign read_cycle = decode_csr_address == 12'hC00;
assign read_cycleh = decode_csr_address == 12'hC80;
assign read_instret = decode_csr_address == 12'hC02;
assign read_instreth = decode_csr_address == 12'hC82;
/* verilator lint_off WIDTH */
assign out_decode_csr_data = read_cycle ? cycle[31:0] :
read_cycleh ? cycle[63:32] :
read_instret ? instret[31:0] :
read_instreth ? instret[63:32] :
{{20{1'b0}}, data_read};
/* verilator lint_on WIDTH */
endmodule // VX_csr_handler

114
rtl/VX_csr_pipe.v
View File

@@ -1,114 +0,0 @@
`include "VX_define.v"
module VX_csr_pipe
#(
parameter CORE_ID = 0
)
(
input wire clk, // Clock
input wire reset,
input wire no_slot_csr,
VX_csr_req_inter VX_csr_req,
VX_wb_inter VX_writeback,
VX_csr_wb_inter VX_csr_wb,
output wire stall_gpr_csr
);
wire[`NT_M1:0] valid_s2;
wire[`NW_M1:0] warp_num_s2;
wire[4:0] rd_s2;
wire[1:0] wb_s2;
wire[4:0] alu_op_s2;
wire is_csr_s2;
wire[11:0] csr_address_s2;
wire[31:0] csr_read_data_s2;
wire[31:0] csr_updated_data_s2;
wire[31:0] csr_read_data_unqual;
wire[31:0] csr_read_data;
assign stall_gpr_csr = no_slot_csr && VX_csr_req.is_csr && |(VX_csr_req.valid);
assign csr_read_data = (csr_address_s2 == VX_csr_req.csr_address) ? csr_updated_data_s2 : csr_read_data_unqual;
wire writeback = |VX_writeback.wb_valid;
VX_csr_data VX_csr_data(
.clk (clk),
.reset (reset),
.in_read_csr_address (VX_csr_req.csr_address),
.in_write_valid (is_csr_s2),
.in_write_csr_data (csr_updated_data_s2),
.in_write_csr_address(csr_address_s2),
.out_read_csr_data (csr_read_data_unqual),
.in_writeback_valid (writeback)
);
reg[31:0] csr_updated_data;
always @(*) begin
case(VX_csr_req.alu_op)
`CSR_ALU_RW: csr_updated_data = VX_csr_req.csr_mask;
`CSR_ALU_RS: csr_updated_data = csr_read_data | VX_csr_req.csr_mask;
`CSR_ALU_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - VX_csr_req.csr_mask);
default: csr_updated_data = 32'hdeadbeef;
endcase
end
wire zero = 0;
VX_generic_register #(.N(32 + 32 + 12 + 1 + 2 + 5 + (`NW_M1+1) + `NT)) csr_reg_s2 (
.clk (clk),
.reset(reset),
.stall(no_slot_csr),
.flush(zero),
.in ({VX_csr_req.valid, VX_csr_req.warp_num, VX_csr_req.rd, VX_csr_req.wb, VX_csr_req.is_csr, VX_csr_req.csr_address, csr_read_data , csr_updated_data }),
.out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_read_data_s2, csr_updated_data_s2})
);
wire[`NT_M1:0][31:0] final_csr_data;
wire[`NT_M1:0][31:0] thread_ids;
wire[`NT_M1:0][31:0] warp_ids;
wire[`NT_M1:0][31:0] warp_idz;
wire[`NT_M1:0][31:0] csr_vec_read_data_s2;
genvar cur_t;
for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin
assign thread_ids[cur_t] = cur_t;
end
genvar cur_tw;
for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin
assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, warp_num_s2};
assign warp_idz[cur_tw] = (warp_num_s2 + (CORE_ID*`NW));
end
genvar cur_v;
for (cur_v = 0; cur_v < `NT; cur_v = cur_v + 1) begin
assign csr_vec_read_data_s2[cur_v] = csr_read_data_s2;
end
wire thread_select = csr_address_s2 == 12'h20;
wire warp_select = csr_address_s2 == 12'h21;
wire warp_id_select = csr_address_s2 == 12'h22;
assign final_csr_data = thread_select ? thread_ids :
warp_select ? warp_ids :
warp_id_select ? warp_idz :
csr_vec_read_data_s2;
assign VX_csr_wb.valid = valid_s2;
assign VX_csr_wb.warp_num = warp_num_s2;
assign VX_csr_wb.rd = rd_s2;
assign VX_csr_wb.wb = wb_s2;
assign VX_csr_wb.csr_result = final_csr_data;
endmodule

39
rtl/VX_csr_wrapper.v
View File

@@ -1,39 +0,0 @@
`include "VX_define.v"
module VX_csr_wrapper (
VX_csr_req_inter VX_csr_req,
VX_csr_wb_inter VX_csr_wb
);
wire[`NT_M1:0][31:0] thread_ids;
wire[`NT_M1:0][31:0] warp_ids;
genvar cur_t, cur_tw;
generate
for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin : thread_ids_init
assign thread_ids[cur_t] = cur_t;
end
for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin : warp_ids_init
assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, VX_csr_req.warp_num};
end
endgenerate
assign VX_csr_wb.valid = VX_csr_req.valid;
assign VX_csr_wb.warp_num = VX_csr_req.warp_num;
assign VX_csr_wb.rd = VX_csr_req.rd;
assign VX_csr_wb.wb = VX_csr_req.wb;
wire thread_select = VX_csr_req.csr_address == 12'h20;
wire warp_select = VX_csr_req.csr_address == 12'h21;
assign VX_csr_wb.csr_result = thread_select ? thread_ids :
warp_select ? warp_ids :
0;
endmodule

361
rtl/VX_decode.v
View File

@@ -1,361 +0,0 @@
`include "VX_define.v"
module VX_decode(
// Fetch Inputs
VX_inst_meta_inter fd_inst_meta_de,
// Outputs
VX_frE_to_bckE_req_inter VX_frE_to_bckE_req,
VX_wstall_inter VX_wstall,
VX_join_inter VX_join,
output wire terminate_sim
);
wire[31:0] in_instruction = fd_inst_meta_de.instruction;
wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc;
wire[`NW_M1:0] in_warp_num = fd_inst_meta_de.warp_num;
assign VX_frE_to_bckE_req.curr_PC = in_curr_PC;
wire[`NT_M1:0] in_valid = fd_inst_meta_de.valid;
wire[6:0] curr_opcode;
wire is_itype;
wire is_rtype;
wire is_stype;
wire is_btype;
wire is_linst;
wire is_jal;
wire is_jalr;
wire is_lui;
wire is_auipc;
wire is_csr;
wire is_csr_immed;
wire is_e_inst;
wire is_gpgpu;
wire is_wspawn;
wire is_tmc;
wire is_split;
wire is_join;
wire is_barrier;
wire[2:0] func3;
wire[6:0] func7;
wire[11:0] u_12;
wire[7:0] jal_b_19_to_12;
wire jal_b_11;
wire[9:0] jal_b_10_to_1;
wire jal_b_20;
wire jal_b_0;
wire[20:0] jal_unsigned_offset;
wire[31:0] jal_1_offset;
wire[11:0] jalr_immed;
wire[31:0] jal_2_offset;
wire jal_sys_cond1;
wire jal_sys_cond2;
wire jal_sys_jal;
wire[31:0] jal_sys_off;
wire csr_cond1;
wire csr_cond2;
wire[11:0] alu_tempp;
wire alu_shift_i;
wire[11:0] alu_shift_i_immed;
wire[1:0] csr_type;
reg[4:0] csr_alu;
reg[4:0] alu_op;
reg[4:0] mul_alu;
reg[19:0] temp_upper_immed;
reg temp_jal;
reg[31:0] temp_jal_offset;
reg[31:0] temp_itype_immed;
reg[2:0] temp_branch_type;
reg temp_branch_stall;
// always @(posedge reset) begin
// end
assign VX_frE_to_bckE_req.valid = fd_inst_meta_de.valid;
assign VX_frE_to_bckE_req.warp_num = in_warp_num;
assign curr_opcode = in_instruction[6:0];
assign VX_frE_to_bckE_req.rd = in_instruction[11:7];
assign VX_frE_to_bckE_req.rs1 = in_instruction[19:15];
assign VX_frE_to_bckE_req.rs2 = in_instruction[24:20];
assign func3 = in_instruction[14:12];
assign func7 = in_instruction[31:25];
assign u_12 = in_instruction[31:20];
assign VX_frE_to_bckE_req.PC_next = in_curr_PC + 32'h4;
// Write Back sigal
assign is_rtype = (curr_opcode == `R_INST);
assign is_linst = (curr_opcode == `L_INST);
assign is_itype = (curr_opcode == `ALU_INST) || is_linst;
assign is_stype = (curr_opcode == `S_INST);
assign is_btype = (curr_opcode == `B_INST);
assign is_jal = (curr_opcode == `JAL_INST);
assign is_jalr = (curr_opcode == `JALR_INST);
assign is_lui = (curr_opcode == `LUI_INST);
assign is_auipc = (curr_opcode == `AUIPC_INST);
assign is_csr = (curr_opcode == `SYS_INST) && (func3 != 0);
assign is_csr_immed = (is_csr) && (func3[2] == 1);
// assign is_e_inst = (curr_opcode == `SYS_INST) && (func3 == 0);
assign is_e_inst = in_instruction == 32'h00000073;
assign is_gpgpu = (curr_opcode == `GPGPU_INST);
assign is_tmc = is_gpgpu && (func3 == 0); // Goes to BE
assign is_wspawn = is_gpgpu && (func3 == 1); // Goes to BE
assign is_barrier = is_gpgpu && (func3 == 4); // Goes to BE
assign is_split = is_gpgpu && (func3 == 2); // Goes to BE
assign is_join = is_gpgpu && (func3 == 3); // Doesn't go to BE
assign VX_join.is_join = is_join;
assign VX_join.join_warp_num = in_warp_num;
assign VX_frE_to_bckE_req.is_wspawn = is_wspawn;
assign VX_frE_to_bckE_req.is_tmc = is_tmc;
assign VX_frE_to_bckE_req.is_split = is_split;
assign VX_frE_to_bckE_req.is_barrier = is_barrier;
assign VX_frE_to_bckE_req.csr_immed = is_csr_immed;
assign VX_frE_to_bckE_req.is_csr = is_csr;
assign VX_frE_to_bckE_req.wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL :
is_linst ? `WB_MEM :
(is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU :
`NO_WB;
assign VX_frE_to_bckE_req.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG;
// MEM signals
assign VX_frE_to_bckE_req.mem_read = (is_linst) ? func3 : `NO_MEM_READ;
assign VX_frE_to_bckE_req.mem_write = (is_stype) ? func3 : `NO_MEM_WRITE;
// UPPER IMMEDIATE
always @(*) begin
case(curr_opcode)
`LUI_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3};
`AUIPC_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3};
default: temp_upper_immed = 20'h0;
endcase // curr_opcode
end
assign VX_frE_to_bckE_req.upper_immed = temp_upper_immed;
assign jal_b_19_to_12 = in_instruction[19:12];
assign jal_b_11 = in_instruction[20];
assign jal_b_10_to_1 = in_instruction[30:21];
assign jal_b_20 = in_instruction[31];
assign jal_b_0 = 1'b0;
assign jal_unsigned_offset = {jal_b_20, jal_b_19_to_12, jal_b_11, jal_b_10_to_1, jal_b_0};
assign jal_1_offset = {{11{jal_b_20}}, jal_unsigned_offset};
assign jalr_immed = {func7, VX_frE_to_bckE_req.rs2};
assign jal_2_offset = {{20{jalr_immed[11]}}, jalr_immed};
assign jal_sys_cond1 = func3 == 3'h0;
assign jal_sys_cond2 = u_12 < 12'h2;
assign jal_sys_jal = (jal_sys_cond1 && jal_sys_cond2) ? 1'b1 : 1'b0;
assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef;
// JAL
always @(*) begin
case(curr_opcode)
`JAL_INST:
begin
temp_jal = 1'b1 && (|in_valid);
temp_jal_offset = jal_1_offset;
end
`JALR_INST:
begin
temp_jal = 1'b1 && (|in_valid);
temp_jal_offset = jal_2_offset;
end
`SYS_INST:
begin
// $display("SYS EBREAK %h", (jal_sys_jal && (|in_valid)) );
temp_jal = jal_sys_jal && (|in_valid);
temp_jal_offset = jal_sys_off;
end
default:
begin
temp_jal = 1'b0 && (|in_valid);
temp_jal_offset = 32'hdeadbeef;
end
endcase
end
assign VX_frE_to_bckE_req.jalQual = is_jal;
assign VX_frE_to_bckE_req.jal = temp_jal;
assign VX_frE_to_bckE_req.jal_offset = temp_jal_offset;
// wire is_ebreak;
// assign is_ebreak = is_e_inst;
wire ebreak = (curr_opcode == `SYS_INST) && (jal_sys_jal && (|in_valid));
assign VX_frE_to_bckE_req.ebreak = ebreak;
wire out_ebreak = ebreak;
assign terminate_sim = is_e_inst;
// CSR
assign csr_cond1 = func3 != 3'h0;
assign csr_cond2 = u_12 >= 12'h2;
assign VX_frE_to_bckE_req.csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55;
// ITYPE IMEED
assign alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5);
assign alu_shift_i_immed = {{7{1'b0}}, VX_frE_to_bckE_req.rs2};
assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12;
always @(*) begin
case(curr_opcode)
`ALU_INST: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp};
`S_INST: temp_itype_immed = {{20{func7[6]}}, func7, VX_frE_to_bckE_req.rd};
`L_INST: temp_itype_immed = {{20{u_12[11]}}, u_12};
`B_INST: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]};
default: temp_itype_immed = 32'hdeadbeef;
endcase
end
assign VX_frE_to_bckE_req.itype_immed = temp_itype_immed;
always @(*) begin
case(curr_opcode)
`B_INST:
begin
// $display("BRANCH IN DECODE");
temp_branch_stall = 1'b1 && (|in_valid);
case(func3)
3'h0: temp_branch_type = `BEQ;
3'h1: temp_branch_type = `BNE;
3'h4: temp_branch_type = `BLT;
3'h5: temp_branch_type = `BGT;
3'h6: temp_branch_type = `BLTU;
3'h7: temp_branch_type = `BGTU;
default: temp_branch_type = `NO_BRANCH;
endcase
end
`JAL_INST:
begin
temp_branch_type = `NO_BRANCH;
temp_branch_stall = 1'b1 && (|in_valid);
end
`JALR_INST:
begin
temp_branch_type = `NO_BRANCH;
temp_branch_stall = 1'b1 && (|in_valid);
end
default:
begin
temp_branch_type = `NO_BRANCH;
temp_branch_stall = 1'b0 && (|in_valid);
end
endcase
end
assign VX_frE_to_bckE_req.branch_type = temp_branch_type;
assign VX_wstall.wstall = (temp_branch_stall || is_tmc || is_split || is_barrier) && (|in_valid);
assign VX_wstall.warp_num = in_warp_num;
always @(*) begin
// ALU OP
case(func3)
3'h0: alu_op = (curr_opcode == `ALU_INST) ? `ADD : (func7 == 7'h0 ? `ADD : `SUB);
3'h1: alu_op = `SLLA;
3'h2: alu_op = `SLT;
3'h3: alu_op = `SLTU;
3'h4: alu_op = `XOR;
3'h5: alu_op = (func7 == 7'h0) ? `SRL : `SRA;
3'h6: alu_op = `OR;
3'h7: alu_op = `AND;
default: alu_op = `NO_ALU;
endcase
end
always @(*) begin
// ALU OP
case(func3)
3'h0: mul_alu = `MUL;
3'h1: mul_alu = `MULH;
3'h2: mul_alu = `MULHSU;
3'h3: mul_alu = `MULHU;
3'h4: mul_alu = `DIV;
3'h5: mul_alu = `DIVU;
3'h6: mul_alu = `REM;
3'h7: mul_alu = `REMU;
default: mul_alu = `NO_ALU;
endcase
end
assign csr_type = func3[1:0];
always @(*) begin
case(csr_type)
2'h1: csr_alu = `CSR_ALU_RW;
2'h2: csr_alu = `CSR_ALU_RS;
2'h3: csr_alu = `CSR_ALU_RC;
default: csr_alu = `NO_ALU;
endcase
end
wire[4:0] temp_final_alu;
assign temp_final_alu = is_btype ? ((VX_frE_to_bckE_req.branch_type < `BLTU) ? `SUB : `SUBU) :
is_lui ? `LUI_ALU :
is_auipc ? `AUIPC_ALU :
is_csr ? csr_alu :
(is_stype || is_linst) ? `ADD :
alu_op;
assign VX_frE_to_bckE_req.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu;
endmodule

736
rtl/VX_define.v
View File

@@ -1,736 +0,0 @@
`ifndef VX_DEFINE
`define VX_DEFINE
`include "./VX_define_synth.v"
`ifndef NT
`define NT 4
`endif
`ifndef NW
`define NW 8
`endif
`ifndef NUMBER_CORES_PER_CLUSTER
`define NUMBER_CORES_PER_CLUSTER 1
`endif
`ifndef NUMBER_CLUSTERS
`define NUMBER_CLUSTERS 1
`endif
// `define QUEUE_FORCE_MLAB 1
`define NT_M1 (`NT-1)
// NW_M1 is actually log2(NW)
`define NW_M1 (`CLOG2(`NW))
// Uncomment the below line if NW=1
// `define ONLY
// `define SYN 1
// `define ASIC 1
// `define SYN_FUNC 1
`ifndef NUM_BARRIERS
`define NUM_BARRIERS 4
`endif
`define R_INST 7'd51
`define L_INST 7'd3
`define ALU_INST 7'd19
`define S_INST 7'd35
`define B_INST 7'd99
`define LUI_INST 7'd55
`define AUIPC_INST 7'd23
`define JAL_INST 7'd111
`define JALR_INST 7'd103
`define SYS_INST 7'd115
`define GPGPU_INST 7'h6b
`define WB_ALU 2'h1
`define WB_MEM 2'h2
`define WB_JAL 2'h3
`define NO_WB 2'h0
`define RS2_IMMED 1
`define RS2_REG 0
`define NO_MEM_READ 3'h7
`define LB_MEM_READ 3'h0
`define LH_MEM_READ 3'h1
`define LW_MEM_READ 3'h2
`define LBU_MEM_READ 3'h4
`define LHU_MEM_READ 3'h5
`define NO_MEM_WRITE 3'h7
`define SB_MEM_WRITE 3'h0
`define SH_MEM_WRITE 3'h1
`define SW_MEM_WRITE 3'h2
`define NO_BRANCH 3'h0
`define BEQ 3'h1
`define BNE 3'h2
`define BLT 3'h3
`define BGT 3'h4
`define BLTU 3'h5
`define BGTU 3'h6
`define NO_ALU 5'd15
`define ADD 5'd0
`define SUB 5'd1
`define SLLA 5'd2
`define SLT 5'd3
`define SLTU 5'd4
`define XOR 5'd5
`define SRL 5'd6
`define SRA 5'd7
`define OR 5'd8
`define AND 5'd9
`define SUBU 5'd10
`define LUI_ALU 5'd11
`define AUIPC_ALU 5'd12
`define CSR_ALU_RW 5'd13
`define CSR_ALU_RS 5'd14
`define CSR_ALU_RC 5'd15
`define MUL 5'd16
`define MULH 5'd17
`define MULHSU 5'd18
`define MULHU 5'd19
`define DIV 5'd20
`define DIVU 5'd21
`define REM 5'd22
`define REMU 5'd23
// WRITEBACK
`define WB_ALU 2'h1
`define WB_MEM 2'h2
`define WB_JAL 2'h3
`define NO_WB 2'h0
// JAL
`define JUMP 1'h1
`define NO_JUMP 1'h0
// STALLS
`define STALL 1'h1
`define NO_STALL 1'h0
`define TAKEN 1'h1
`define NOT_TAKEN 1'h0
`define ZERO_REG 5'h0
`define CLOG2(x) \
(x <= 2) ? 1 : \
(x <= 4) ? 2 : \
(x <= 8) ? 3 : \
(x <= 16) ? 4 : \
(x <= 32) ? 5 : \
(x <= 64) ? 6 : \
(x <= 128) ? 7 : \
(x <= 256) ? 8 : \
(x <= 512) ? 9 : \
(x <= 1024) ? 10 : \
-199
`ifndef NUMBER_CORES
`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
`endif
// `define SINGLE_CORE_BENCH
`ifndef GLOBAL_BLOCK_SIZE_BYTES
`define GLOBAL_BLOCK_SIZE_BYTES 16
`endif
// ========================================= Dcache Configurable Knobs =========================================
// General Cache Knobs
// Size of cache in bytes
`ifndef DCACHE_SIZE_BYTES
`define DCACHE_SIZE_BYTES 2048
`endif
// Size of line inside a bank in bytes
`ifndef DBANK_LINE_SIZE_BYTES
`define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`endif
// Number of banks {1, 2, 4, 8,...}
`ifndef DNUMBER_BANKS
`define DNUMBER_BANKS 8
`endif
// Size of a word in bytes
`ifndef DWORD_SIZE_BYTES
`define DWORD_SIZE_BYTES 4
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef DNUMBER_REQUESTS
`define DNUMBER_REQUESTS `NT
`endif
// Number of cycles to complete stage 1 (read from memory)
`ifndef DSTAGE_1_CYCLES
`define DSTAGE_1_CYCLES 1
`endif
// Function ID
`ifndef DFUNC_ID
`define DFUNC_ID 0
`endif
// Bank Number of words in a line
`ifndef DBANK_LINE_SIZE_WORDS
`define DBANK_LINE_SIZE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES)
`endif
// Bank Number of words range
`ifndef DBANK_LINE_SIZE_RNG
`define DBANK_LINE_SIZE_RNG `DBANK_LINE_SIZE_WORDS-1:0
`endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`ifndef DREQQ_SIZE
`define DREQQ_SIZE `NW
`endif
// Miss Reserv Queue Knob
`ifndef DMRVQ_SIZE
`define DMRVQ_SIZE (`NW*`NT)
`endif
// Dram Fill Rsp Queue Size
`ifndef DDFPQ_SIZE
`define DDFPQ_SIZE 32
`endif
// Snoop Req Queue
`ifndef DSNRQ_SIZE
`define DSNRQ_SIZE 32
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`ifndef DCWBQ_SIZE
`define DCWBQ_SIZE `DREQQ_SIZE
`endif
// Dram Writeback Queue Size
`ifndef DDWBQ_SIZE
`define DDWBQ_SIZE 4
`endif
// Dram Fill Req Queue Size
`ifndef DDFQQ_SIZE
`define DDFQQ_SIZE `DREQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`ifndef DLLVQ_SIZE
`define DLLVQ_SIZE 0
`endif
// Fill Forward SNP Queue
`ifndef DFFSQ_SIZE
`define DFFSQ_SIZE 32
`endif
// Prefetcher
`ifndef DPRFQ_SIZE
`define DPRFQ_SIZE 32
`endif
`ifndef DPRFQ_STRIDE
`define DPRFQ_STRIDE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef DFILL_INVALIDAOR_SIZE
`define DFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
`ifndef DSIMULATED_DRAM_LATENCY_CYCLES
`define DSIMULATED_DRAM_LATENCY_CYCLES 2
`endif
// ========================================= Icache Configurable Knobs =========================================
// General Cache Knobs
// Size of cache in bytes
`ifndef ICACHE_SIZE_BYTES
`define ICACHE_SIZE_BYTES 4096
`endif
// Size of line inside a bank in bytes
`ifndef IBANK_LINE_SIZE_BYTES
`define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`endif
// Number of banks {1, 2, 4, 8,...}
`ifndef INUMBER_BANKS
`define INUMBER_BANKS 8
`endif
// Size of a word in bytes
`ifndef IWORD_SIZE_BYTES
`define IWORD_SIZE_BYTES 4
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef INUMBER_REQUESTS
`define INUMBER_REQUESTS 1
`endif
// Number of cycles to complete stage 1 (read from memory)
`ifndef ISTAGE_1_CYCLES
`define ISTAGE_1_CYCLES 1
`endif
// Function ID
`ifndef IFUNC_ID
`define IFUNC_ID 1
`endif
// Bank Number of words in a line
`ifndef IBANK_LINE_SIZE_WORDS
`define IBANK_LINE_SIZE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES)
`endif
// Bank Number of words range
`ifndef IBANK_LINE_SIZE_RNG
`define IBANK_LINE_SIZE_RNG `IBANK_LINE_SIZE_WORDS-1:0
`endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`ifndef IREQQ_SIZE
`define IREQQ_SIZE `NW
`endif
// Miss Reserv Queue Knob
`ifndef IMRVQ_SIZE
`define IMRVQ_SIZE `IREQQ_SIZE
`endif
// Dram Fill Rsp Queue Size
`ifndef IDFPQ_SIZE
`define IDFPQ_SIZE 32
`endif
// Snoop Req Queue
`ifndef ISNRQ_SIZE
`define ISNRQ_SIZE 32
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`ifndef ICWBQ_SIZE
`define ICWBQ_SIZE `IREQQ_SIZE
`endif
// Dram Writeback Queue Size
`ifndef IDWBQ_SIZE
`define IDWBQ_SIZE 16
`endif
// Dram Fill Req Queue Size
`ifndef IDFQQ_SIZE
`define IDFQQ_SIZE `IREQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`ifndef ILLVQ_SIZE
`define ILLVQ_SIZE 16
`endif
// Fill Forward SNP Queue
`ifndef IFFSQ_SIZE
`define IFFSQ_SIZE 8
`endif
// Prefetcher
`ifndef IPRFQ_SIZE
`define IPRFQ_SIZE 32
`endif
`ifndef IPRFQ_STRIDE
`define IPRFQ_STRIDE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef IFILL_INVALIDAOR_SIZE
`define IFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
`ifndef ISIMULATED_DRAM_LATENCY_CYCLES
`define ISIMULATED_DRAM_LATENCY_CYCLES 2
`endif
// ========================================= SM Configurable Knobs =========================================
// General Cache Knobs
// Size of cache in bytes
`ifndef SCACHE_SIZE_BYTES
`define SCACHE_SIZE_BYTES 1024
`endif
// Size of line inside a bank in bytes
`ifndef SBANK_LINE_SIZE_BYTES
`define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`endif
// Number of banks {1, 2, 4, 8,...}
`ifndef SNUMBER_BANKS
`define SNUMBER_BANKS 8
`endif
// Size of a word in bytes
`ifndef SWORD_SIZE_BYTES
`define SWORD_SIZE_BYTES 4
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef SNUMBER_REQUESTS
`define SNUMBER_REQUESTS `NT
`endif
// Number of cycles to complete stage 1 (read from memory)
`ifndef SSTAGE_1_CYCLES
`define SSTAGE_1_CYCLES 1
`endif
// Function ID
`ifndef SFUNC_ID
`define SFUNC_ID 2
`endif
// Bank Number of words in a line
`ifndef SBANK_LINE_SIZE_WORDS
`define SBANK_LINE_SIZE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES)
`endif
`ifndef SBANK_LINE_SIZE_RNG
`define SBANK_LINE_SIZE_RNG `SBANK_LINE_SIZE_WORDS-1:0
`endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`ifndef SREQQ_SIZE
`define SREQQ_SIZE `NW
`endif
// Miss Reserv Queue Knob
`ifndef SMRVQ_SIZE
`define SMRVQ_SIZE `SREQQ_SIZE
`endif
// Dram Fill Rsp Queue Size
`ifndef SDFPQ_SIZE
`define SDFPQ_SIZE 0
`endif
// Snoop Req Queue
`ifndef SSNRQ_SIZE
`define SSNRQ_SIZE 16
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`ifndef SCWBQ_SIZE
`define SCWBQ_SIZE `SREQQ_SIZE
`endif
// Dram Writeback Queue Size
`ifndef SDWBQ_SIZE
`define SDWBQ_SIZE 16
`endif
// Dram Fill Req Queue Size
`ifndef SDFQQ_SIZE
`define SDFQQ_SIZE 16
`endif
// Lower Level Cache Hit Queue Size
`ifndef SLLVQ_SIZE
`define SLLVQ_SIZE 16
`endif
// Fill Forward SNP Queue
`ifndef SFFSQ_SIZE
`define SFFSQ_SIZE 16
`endif
// Prefetcher
`ifndef SPRFQ_SIZE
`define SPRFQ_SIZE 4
`endif
`ifndef SPRFQ_STRIDE
`define SPRFQ_STRIDE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef SFILL_INVALIDAOR_SIZE
`define SFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
`ifndef SSIMULATED_DRAM_LATENCY_CYCLES
`define SSIMULATED_DRAM_LATENCY_CYCLES 2
`endif
// ========================================= L2cache Configurable Knobs =========================================
// General Cache Knobs
// Size of cache in bytes
`ifndef LLCACHE_SIZE_BYTES
`define LLCACHE_SIZE_BYTES 4096
`endif
// Size of line inside a bank in bytes
`ifndef LLBANK_LINE_SIZE_BYTES
`define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`endif
// Number of banks {1, 2, 4, 8,...}
`ifndef LLNUMBER_BANKS
`define LLNUMBER_BANKS 8
`endif
// Size of a word in bytes
`ifndef LLWORD_SIZE_BYTES
`define LLWORD_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES)
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef LLNUMBER_REQUESTS
`define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER)
`endif
// Number of cycles to complete stage 1 (read from memory)
`ifndef LLSTAGE_1_CYCLES
`define LLSTAGE_1_CYCLES 1
`endif
// Function ID
`define LLFUNC_ID 3
// Bank Number of words in a line
`ifndef LLBANK_LINE_SIZE_WORDS
`define LLBANK_LINE_SIZE_WORDS (`LLBANK_LINE_SIZE_BYTES / `LLWORD_SIZE_BYTES)
`endif
`ifndef LLBANK_LINE_SIZE_RNG
`define LLBANK_LINE_SIZE_RNG `LLBANK_LINE_SIZE_WORDS-1:0
`endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`ifndef LLREQQ_SIZE
`define LLREQQ_SIZE 32
`endif
// Miss Reserv Queue Knob
`ifndef LLMRVQ_SIZE
`define LLMRVQ_SIZE 32
`endif
// Dram Fill Rsp Queue Size
`ifndef LLDFPQ_SIZE
`define LLDFPQ_SIZE 32
`endif
// Snoop Req Queue
`ifndef LLSNRQ_SIZE
`define LLSNRQ_SIZE 32
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`ifndef LLCWBQ_SIZE
`define LLCWBQ_SIZE `LLREQQ_SIZE
`endif
// Dram Writeback Queue Size
`ifndef LLDWBQ_SIZE
`define LLDWBQ_SIZE 16
`endif
// Dram Fill Req Queue Size
`ifndef LLDFQQ_SIZE
`define LLDFQQ_SIZE `LLREQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`ifndef LLLLVQ_SIZE
`define LLLLVQ_SIZE 32
`endif
// Fill Forward SNP Queue
`ifndef LLFFSQ_SIZE
`define LLFFSQ_SIZE 32
`endif
// Prefetcher
`ifndef LLPRFQ_SIZE
`define LLPRFQ_SIZE 32
`endif
`ifndef LLPRFQ_STRIDE
`define LLPRFQ_STRIDE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef LLFILL_INVALIDAOR_SIZE
`define LLFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
`ifndef LLSIMULATED_DRAM_LATENCY_CYCLES
`define LLSIMULATED_DRAM_LATENCY_CYCLES 2
`endif
// ========================================= L3cache Configurable Knobs =========================================
// General Cache Knobs
// Size of cache in bytes
`ifndef L3CACHE_SIZE_BYTES
`define L3CACHE_SIZE_BYTES 8192
`endif
// Size of line inside a bank in bytes
`ifndef L3BANK_LINE_SIZE_BYTES
`define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`endif
// Number of banks {1, 2, 4, 8,...}
`ifndef L3NUMBER_BANKS
`define L3NUMBER_BANKS 8
`endif
// Size of a word in bytes
`ifndef L3WORD_SIZE_BYTES
`define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES)
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef L3NUMBER_REQUESTS
`define L3NUMBER_REQUESTS (`NUMBER_CLUSTERS)
`endif
// Number of cycles to complete stage 1 (read from memory)
`ifndef L3STAGE_1_CYCLES
`define L3STAGE_1_CYCLES 1
`endif
// Function ID
`define L3FUNC_ID 3
// Bank Number of words in a line
`ifndef L3BANK_LINE_SIZE_WORDS
`define L3BANK_LINE_SIZE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES)
`endif
`ifndef L3BANK_LINE_SIZE_RNG
`define L3BANK_LINE_SIZE_RNG `L3BANK_LINE_SIZE_WORDS-1:0
`endif
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
`ifndef L3REQQ_SIZE
`define L3REQQ_SIZE 32
`endif
// Miss Reserv Queue Knob
`ifndef L3MRVQ_SIZE
`define L3MRVQ_SIZE `L3REQQ_SIZE
`endif
// Dram Fill Rsp Queue Size
`ifndef L3DFPQ_SIZE
`define L3DFPQ_SIZE 32
`endif
// Snoop Req Queue
`ifndef L3SNRQ_SIZE
`define L3SNRQ_SIZE 32
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
`ifndef L3CWBQ_SIZE
`define L3CWBQ_SIZE `L3REQQ_SIZE
`endif
// Dram Writeback Queue Size
`ifndef L3DWBQ_SIZE
`define L3DWBQ_SIZE 16
`endif
// Dram Fill Req Queue Size
`ifndef L3DFQQ_SIZE
`define L3DFQQ_SIZE `L3REQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`ifndef L3LLVQ_SIZE
`define L3LLVQ_SIZE 0
`endif
// Fill Forward SNP Queue
`ifndef L3FFSQ_SIZE
`define L3FFSQ_SIZE 8
`endif
// Prefetcher
`ifndef L3PRFQ_SIZE
`define L3PRFQ_SIZE 32
`endif
`ifndef L3PRFQ_STRIDE
`define L3PRFQ_STRIDE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef L3FILL_INVALIDAOR_SIZE
`define L3FILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
`ifndef L3SIMULATED_DRAM_LATENCY_CYCLES
`define L3SIMULATED_DRAM_LATENCY_CYCLES 2
`endif
// VX_DEFINE
`endif

342
rtl/VX_dmem_controller.v
View File

@@ -1,342 +0,0 @@
`include "VX_define.v"
module VX_dmem_controller (
input wire clk,
input wire reset,
// Dram <-> Dcache
VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req,
VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res,
VX_gpu_snp_req_rsp VX_gpu_dcache_snp_req,
// Dram <-> Icache
VX_gpu_dcache_dram_req_inter VX_gpu_icache_dram_req,
VX_gpu_dcache_dram_res_inter VX_gpu_icache_dram_res,
VX_gpu_snp_req_rsp VX_gpu_icache_snp_req,
// Core <-> Dcache
VX_gpu_dcache_res_inter VX_dcache_rsp,
VX_gpu_dcache_req_inter VX_dcache_req,
// Core <-> Icache
VX_gpu_dcache_res_inter VX_icache_rsp,
VX_gpu_dcache_req_inter VX_icache_req
);
VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp_smem();
VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_smem();
VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp_dcache();
VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_dcache();
wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF;
wire dcache_wants_wb = (|VX_dcache_rsp_dcache.core_wb_valid);
// Dcache Request
assign VX_dcache_req_dcache.core_req_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}};
assign VX_dcache_req_dcache.core_req_addr = VX_dcache_req.core_req_addr;
assign VX_dcache_req_dcache.core_req_writedata = VX_dcache_req.core_req_writedata;
assign VX_dcache_req_dcache.core_req_mem_read = VX_dcache_req.core_req_mem_read;
assign VX_dcache_req_dcache.core_req_mem_write = VX_dcache_req.core_req_mem_write;
assign VX_dcache_req_dcache.core_req_rd = VX_dcache_req.core_req_rd;
assign VX_dcache_req_dcache.core_req_wb = VX_dcache_req.core_req_wb;
assign VX_dcache_req_dcache.core_req_warp_num = VX_dcache_req.core_req_warp_num;
assign VX_dcache_req_dcache.core_req_pc = VX_dcache_req.core_req_pc;
assign VX_dcache_req_dcache.core_no_wb_slot = VX_dcache_req.core_no_wb_slot;
// Shred Memory Request
assign VX_dcache_req_smem.core_req_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}};
assign VX_dcache_req_smem.core_req_addr = VX_dcache_req.core_req_addr;
assign VX_dcache_req_smem.core_req_writedata = VX_dcache_req.core_req_writedata;
assign VX_dcache_req_smem.core_req_mem_read = VX_dcache_req.core_req_mem_read;
assign VX_dcache_req_smem.core_req_mem_write = VX_dcache_req.core_req_mem_write;
assign VX_dcache_req_smem.core_req_rd = VX_dcache_req.core_req_rd;
assign VX_dcache_req_smem.core_req_wb = VX_dcache_req.core_req_wb;
assign VX_dcache_req_smem.core_req_warp_num = VX_dcache_req.core_req_warp_num;
assign VX_dcache_req_smem.core_req_pc = VX_dcache_req.core_req_pc;
assign VX_dcache_req_smem.core_no_wb_slot = VX_dcache_req.core_no_wb_slot || dcache_wants_wb;
// Dcache Response
assign VX_dcache_rsp.core_wb_valid = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_valid : VX_dcache_rsp_smem.core_wb_valid;
assign VX_dcache_rsp.core_wb_req_rd = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_req_rd : VX_dcache_rsp_smem.core_wb_req_rd;
assign VX_dcache_rsp.core_wb_req_wb = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_req_wb : VX_dcache_rsp_smem.core_wb_req_wb;
assign VX_dcache_rsp.core_wb_warp_num = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_warp_num : VX_dcache_rsp_smem.core_wb_warp_num;
assign VX_dcache_rsp.core_wb_readdata = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_readdata : VX_dcache_rsp_smem.core_wb_readdata;
assign VX_dcache_rsp.core_wb_pc = dcache_wants_wb ? VX_dcache_rsp_dcache.core_wb_pc : VX_dcache_rsp_smem.core_wb_pc;
assign VX_dcache_rsp.delay_req = to_shm ? VX_dcache_rsp_smem.delay_req : VX_dcache_rsp_dcache.delay_req;
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_smem_dram_req();
VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_smem_dram_res();
VX_cache #(
.CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`SBANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (`SNUMBER_BANKS),
.WORD_SIZE_BYTES (`SWORD_SIZE_BYTES),
.NUMBER_REQUESTS (`SNUMBER_REQUESTS),
.STAGE_1_CYCLES (`SSTAGE_1_CYCLES),
.FUNC_ID (`SFUNC_ID),
.REQQ_SIZE (`SREQQ_SIZE),
.MRVQ_SIZE (`SMRVQ_SIZE),
.DFPQ_SIZE (`SDFPQ_SIZE),
.SNRQ_SIZE (`SSNRQ_SIZE),
.CWBQ_SIZE (`SCWBQ_SIZE),
.DWBQ_SIZE (`SDWBQ_SIZE),
.DFQQ_SIZE (`SDFQQ_SIZE),
.LLVQ_SIZE (`SLLVQ_SIZE),
.FFSQ_SIZE (`SFFSQ_SIZE),
.PRFQ_SIZE (`SPRFQ_SIZE),
.PRFQ_STRIDE (`SPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`SSIMULATED_DRAM_LATENCY_CYCLES)
)
gpu_smem
(
.clk (clk),
.reset (reset),
// Core req
.core_req_valid (VX_dcache_req_smem.core_req_valid),
.core_req_addr (VX_dcache_req_smem.core_req_addr),
.core_req_writedata(VX_dcache_req_smem.core_req_writedata),
.core_req_mem_read (VX_dcache_req_smem.core_req_mem_read),
.core_req_mem_write(VX_dcache_req_smem.core_req_mem_write),
.core_req_rd (VX_dcache_req_smem.core_req_rd),
.core_req_wb (VX_dcache_req_smem.core_req_wb),
.core_req_warp_num (VX_dcache_req_smem.core_req_warp_num),
.core_req_pc (VX_dcache_req_smem.core_req_pc),
// Delay Core Req
.delay_req (VX_dcache_rsp_smem.delay_req),
// Core Cache Can't WB
.core_no_wb_slot (VX_dcache_req_smem.core_no_wb_slot),
// Cache CWB
.core_wb_valid (VX_dcache_rsp_smem.core_wb_valid),
.core_wb_req_rd (VX_dcache_rsp_smem.core_wb_req_rd),
.core_wb_req_wb (VX_dcache_rsp_smem.core_wb_req_wb),
.core_wb_warp_num (VX_dcache_rsp_smem.core_wb_warp_num),
.core_wb_readdata (VX_dcache_rsp_smem.core_wb_readdata),
.core_wb_pc (VX_dcache_rsp_smem.core_wb_pc),
.core_wb_address (),
// DRAM response
.dram_fill_rsp (VX_gpu_smem_dram_res.dram_fill_rsp),
.dram_fill_rsp_addr(VX_gpu_smem_dram_res.dram_fill_rsp_addr),
.dram_fill_rsp_data(VX_gpu_smem_dram_res.dram_fill_rsp_data),
// DRAM accept response
.dram_fill_accept (VX_gpu_smem_dram_req.dram_fill_accept),
// DRAM Req
.dram_req (VX_gpu_smem_dram_req.dram_req),
.dram_req_write (VX_gpu_smem_dram_req.dram_req_write),
.dram_req_read (VX_gpu_smem_dram_req.dram_req_read),
.dram_req_addr (VX_gpu_smem_dram_req.dram_req_addr),
.dram_req_size (VX_gpu_smem_dram_req.dram_req_size),
.dram_req_data (VX_gpu_smem_dram_req.dram_req_data),
.dram_req_delay (1),
// Snoop Response
.dram_req_because_of_wb(VX_gpu_smem_dram_req.dram_because_of_snp),
.dram_snp_full (VX_gpu_smem_dram_req.dram_snp_full),
// Snoop Request
.snp_req (0),
.snp_req_addr (0),
.snp_req_delay (),
// Snoop Forward
.snp_fwd (),
.snp_fwd_addr (),
.snp_fwd_delay (0)
);
VX_cache #(
.CACHE_SIZE_BYTES (`DCACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`DBANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (`DNUMBER_BANKS),
.WORD_SIZE_BYTES (`DWORD_SIZE_BYTES),
.NUMBER_REQUESTS (`DNUMBER_REQUESTS),
.STAGE_1_CYCLES (`DSTAGE_1_CYCLES),
.FUNC_ID (`DFUNC_ID),
.REQQ_SIZE (`DREQQ_SIZE),
.MRVQ_SIZE (`DMRVQ_SIZE),
.DFPQ_SIZE (`DDFPQ_SIZE),
.SNRQ_SIZE (`DSNRQ_SIZE),
.CWBQ_SIZE (`DCWBQ_SIZE),
.DWBQ_SIZE (`DDWBQ_SIZE),
.DFQQ_SIZE (`DDFQQ_SIZE),
.LLVQ_SIZE (`DLLVQ_SIZE),
.FFSQ_SIZE (`DFFSQ_SIZE),
.PRFQ_SIZE (`DPRFQ_SIZE),
.PRFQ_STRIDE (`DPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`DSIMULATED_DRAM_LATENCY_CYCLES)
)
gpu_dcache
(
.clk (clk),
.reset (reset),
// Core req
.core_req_valid (VX_dcache_req_dcache.core_req_valid),
.core_req_addr (VX_dcache_req_dcache.core_req_addr),
.core_req_writedata(VX_dcache_req_dcache.core_req_writedata),
.core_req_mem_read (VX_dcache_req_dcache.core_req_mem_read),
.core_req_mem_write(VX_dcache_req_dcache.core_req_mem_write),
.core_req_rd (VX_dcache_req_dcache.core_req_rd),
.core_req_wb (VX_dcache_req_dcache.core_req_wb),
.core_req_warp_num (VX_dcache_req_dcache.core_req_warp_num),
.core_req_pc (VX_dcache_req_dcache.core_req_pc),
// Delay Core Req
.delay_req (VX_dcache_rsp_dcache.delay_req),
// Core Cache Can't WB
.core_no_wb_slot (VX_dcache_req_dcache.core_no_wb_slot),
// Cache CWB
.core_wb_valid (VX_dcache_rsp_dcache.core_wb_valid),
.core_wb_req_rd (VX_dcache_rsp_dcache.core_wb_req_rd),
.core_wb_req_wb (VX_dcache_rsp_dcache.core_wb_req_wb),
.core_wb_warp_num (VX_dcache_rsp_dcache.core_wb_warp_num),
.core_wb_readdata (VX_dcache_rsp_dcache.core_wb_readdata),
.core_wb_pc (VX_dcache_rsp_dcache.core_wb_pc),
.core_wb_address (),
// DRAM response
.dram_fill_rsp (VX_gpu_dcache_dram_res.dram_fill_rsp),
.dram_fill_rsp_addr(VX_gpu_dcache_dram_res.dram_fill_rsp_addr),
.dram_fill_rsp_data(VX_gpu_dcache_dram_res.dram_fill_rsp_data),
// DRAM accept response
.dram_fill_accept (VX_gpu_dcache_dram_req.dram_fill_accept),
// DRAM Req
.dram_req (VX_gpu_dcache_dram_req.dram_req),
.dram_req_write (VX_gpu_dcache_dram_req.dram_req_write),
.dram_req_read (VX_gpu_dcache_dram_req.dram_req_read),
.dram_req_addr (VX_gpu_dcache_dram_req.dram_req_addr),
.dram_req_size (VX_gpu_dcache_dram_req.dram_req_size),
.dram_req_data (VX_gpu_dcache_dram_req.dram_req_data),
.dram_req_delay (VX_gpu_dcache_dram_req.dram_req_delay),
// Snoop Response
.dram_req_because_of_wb(VX_gpu_dcache_dram_req.dram_because_of_snp),
.dram_snp_full (VX_gpu_dcache_dram_req.dram_snp_full),
// Snoop Request
.snp_req (VX_gpu_dcache_snp_req.snp_req),
.snp_req_addr (VX_gpu_dcache_snp_req.snp_req_addr),
.snp_req_delay (VX_gpu_dcache_snp_req.snp_delay),
// Snoop Forward
.snp_fwd (),
.snp_fwd_addr (),
.snp_fwd_delay (0)
);
VX_cache #(
.CACHE_SIZE_BYTES (`ICACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`IBANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (`INUMBER_BANKS),
.WORD_SIZE_BYTES (`IWORD_SIZE_BYTES),
.NUMBER_REQUESTS (`INUMBER_REQUESTS),
.STAGE_1_CYCLES (`ISTAGE_1_CYCLES),
.FUNC_ID (`IFUNC_ID),
.REQQ_SIZE (`IREQQ_SIZE),
.MRVQ_SIZE (`IMRVQ_SIZE),
.DFPQ_SIZE (`IDFPQ_SIZE),
.SNRQ_SIZE (`ISNRQ_SIZE),
.CWBQ_SIZE (`ICWBQ_SIZE),
.DWBQ_SIZE (`IDWBQ_SIZE),
.DFQQ_SIZE (`IDFQQ_SIZE),
.LLVQ_SIZE (`ILLVQ_SIZE),
.FFSQ_SIZE (`IFFSQ_SIZE),
.PRFQ_SIZE (`IPRFQ_SIZE),
.PRFQ_STRIDE (`IPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`ISIMULATED_DRAM_LATENCY_CYCLES)
)
gpu_icache
(
.clk (clk),
.reset (reset),
// Core req
.core_req_valid (VX_icache_req.core_req_valid),
.core_req_addr (VX_icache_req.core_req_addr),
.core_req_writedata(VX_icache_req.core_req_writedata),
.core_req_mem_read (VX_icache_req.core_req_mem_read),
.core_req_mem_write(VX_icache_req.core_req_mem_write),
.core_req_rd (VX_icache_req.core_req_rd),
.core_req_wb (VX_icache_req.core_req_wb),
.core_req_warp_num (VX_icache_req.core_req_warp_num),
.core_req_pc (VX_icache_req.core_req_pc),
// Delay Core Req
.delay_req (VX_icache_rsp.delay_req),
// Core Cache Can't WB
.core_no_wb_slot (VX_icache_req.core_no_wb_slot),
// Cache CWB
.core_wb_valid (VX_icache_rsp.core_wb_valid),
.core_wb_req_rd (VX_icache_rsp.core_wb_req_rd),
.core_wb_req_wb (VX_icache_rsp.core_wb_req_wb),
.core_wb_warp_num (VX_icache_rsp.core_wb_warp_num),
.core_wb_readdata (VX_icache_rsp.core_wb_readdata),
.core_wb_pc (VX_icache_rsp.core_wb_pc),
.core_wb_address (),
// DRAM response
.dram_fill_rsp (VX_gpu_icache_dram_res.dram_fill_rsp),
.dram_fill_rsp_addr(VX_gpu_icache_dram_res.dram_fill_rsp_addr),
.dram_fill_rsp_data(VX_gpu_icache_dram_res.dram_fill_rsp_data),
// DRAM accept response
.dram_fill_accept (VX_gpu_icache_dram_req.dram_fill_accept),
// DRAM Req
.dram_req (VX_gpu_icache_dram_req.dram_req),
.dram_req_write (VX_gpu_icache_dram_req.dram_req_write),
.dram_req_read (VX_gpu_icache_dram_req.dram_req_read),
.dram_req_addr (VX_gpu_icache_dram_req.dram_req_addr),
.dram_req_size (VX_gpu_icache_dram_req.dram_req_size),
.dram_req_data (VX_gpu_icache_dram_req.dram_req_data),
.dram_req_delay (VX_gpu_icache_dram_req.dram_req_delay),
// Snoop Response
.dram_req_because_of_wb(VX_gpu_icache_dram_req.dram_because_of_snp),
.dram_snp_full (VX_gpu_icache_dram_req.dram_snp_full),
// Snoop Request
.snp_req (VX_gpu_icache_snp_req.snp_req),
.snp_req_addr (VX_gpu_icache_snp_req.snp_req_addr),
.snp_req_delay (VX_gpu_icache_snp_req.snp_delay),
// Snoop Forward
.snp_fwd (),
.snp_fwd_addr (),
.snp_fwd_delay (0)
);
endmodule

176
rtl/VX_execute_unit.v
View File

@@ -1,176 +0,0 @@
`include "VX_define.v"
module VX_execute_unit (
input wire clk,
input wire reset,
// Request
VX_exec_unit_req_inter VX_exec_unit_req,
// Output
// Writeback
VX_inst_exec_wb_inter VX_inst_exec_wb,
// JAL Response
VX_jal_response_inter VX_jal_rsp,
// Branch Response
VX_branch_response_inter VX_branch_rsp,
input wire no_slot_exec,
output wire out_delay
);
wire[`NT_M1:0][31:0] in_a_reg_data;
wire[`NT_M1:0][31:0] in_b_reg_data;
wire[4:0] in_alu_op;
wire in_rs2_src;
wire[31:0] in_itype_immed;
wire[2:0] in_branch_type;
wire[19:0] in_upper_immed;
wire in_jal;
wire[31:0] in_jal_offset;
wire[31:0] in_curr_PC;
assign in_a_reg_data = VX_exec_unit_req.a_reg_data;
assign in_b_reg_data = VX_exec_unit_req.b_reg_data;
assign in_alu_op = VX_exec_unit_req.alu_op;
assign in_rs2_src = VX_exec_unit_req.rs2_src;
assign in_itype_immed = VX_exec_unit_req.itype_immed;
assign in_branch_type = VX_exec_unit_req.branch_type;
assign in_upper_immed = VX_exec_unit_req.upper_immed;
assign in_jal = VX_exec_unit_req.jal;
assign in_jal_offset = VX_exec_unit_req.jal_offset;
assign in_curr_PC = VX_exec_unit_req.curr_PC;
wire[`NT_M1:0][31:0] alu_result;
wire[`NT_M1:0] alu_stall;
genvar index_out_reg;
generate
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) begin : alu_defs
VX_alu vx_alu(
.clk(clk),
.reset(reset),
// .in_reg_data (in_reg_data[1:0]),
.in_1 (in_a_reg_data[index_out_reg]),
.in_2 (in_b_reg_data[index_out_reg]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
.in_alu_op (in_alu_op),
.in_curr_PC (in_curr_PC),
.out_alu_result(alu_result[index_out_reg]),
.out_alu_stall(alu_stall[index_out_reg])
);
end
endgenerate
wire internal_stall;
assign internal_stall = |alu_stall;
assign out_delay = no_slot_exec || internal_stall;
wire [$clog2(`NT)-1:0] jal_branch_use_index;
wire jal_branch_found_valid;
VX_generic_priority_encoder #(.N(`NT)) choose_alu_result(
.valids(VX_exec_unit_req.valid),
.index (jal_branch_use_index),
.found (jal_branch_found_valid)
);
wire[31:0] branch_use_alu_result = alu_result[jal_branch_use_index];
reg temp_branch_dir;
always @(*)
begin
case(VX_exec_unit_req.branch_type)
`BEQ: temp_branch_dir = (branch_use_alu_result == 0) ? `TAKEN : `NOT_TAKEN;
`BNE: temp_branch_dir = (branch_use_alu_result == 0) ? `NOT_TAKEN : `TAKEN;
`BLT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN;
`BGT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN;
`BLTU: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN;
`BGTU: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN;
`NO_BRANCH: temp_branch_dir = `NOT_TAKEN;
default: temp_branch_dir = `NOT_TAKEN;
endcase // in_branch_type
end
wire[`NT_M1:0][31:0] duplicate_PC_data;
genvar i;
generate
for (i = 0; i < `NT; i=i+1) begin : pc_data_setup
assign duplicate_PC_data[i] = VX_exec_unit_req.PC_next;
end
endgenerate
// VX_inst_exec_wb_inter VX_inst_exec_wb_temp();
// JAL Response
VX_jal_response_inter VX_jal_rsp_temp();
// Branch Response
VX_branch_response_inter VX_branch_rsp_temp();
// Actual Writeback
assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd;
assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb;
assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid & {`NT{!internal_stall}};
assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num;
assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result;
assign VX_inst_exec_wb.exec_wb_pc = in_curr_PC;
// Jal rsp
assign VX_jal_rsp_temp.jal = in_jal;
assign VX_jal_rsp_temp.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset);
assign VX_jal_rsp_temp.jal_warp_num = VX_exec_unit_req.warp_num;
// Branch rsp
assign VX_branch_rsp_temp.valid_branch = (VX_exec_unit_req.branch_type != `NO_BRANCH) && (|VX_exec_unit_req.valid);
assign VX_branch_rsp_temp.branch_dir = temp_branch_dir;
assign VX_branch_rsp_temp.branch_warp_num = VX_exec_unit_req.warp_num;
assign VX_branch_rsp_temp.branch_dest = $signed(VX_exec_unit_req.curr_PC) + ($signed(VX_exec_unit_req.itype_immed) << 1); // itype_immed = branch_offset
wire zero = 0;
// VX_generic_register #(.N(174)) exec_reg(
// .clk (clk),
// .reset(reset),
// .stall(zero),
// .flush(zero),
// .in ({VX_inst_exec_wb_temp.rd, VX_inst_exec_wb_temp.wb, VX_inst_exec_wb_temp.wb_valid, VX_inst_exec_wb_temp.wb_warp_num, VX_inst_exec_wb_temp.alu_result, VX_inst_exec_wb_temp.exec_wb_pc}),
// .out ({VX_inst_exec_wb.rd , VX_inst_exec_wb.wb , VX_inst_exec_wb.wb_valid , VX_inst_exec_wb.wb_warp_num , VX_inst_exec_wb.alu_result , VX_inst_exec_wb.exec_wb_pc })
// );
VX_generic_register #(.N(33 + `NW_M1 + 1)) jal_reg(
.clk (clk),
.reset(reset),
.stall(zero),
.flush(zero),
.in ({VX_jal_rsp_temp.jal, VX_jal_rsp_temp.jal_dest, VX_jal_rsp_temp.jal_warp_num}),
.out ({VX_jal_rsp.jal , VX_jal_rsp.jal_dest , VX_jal_rsp.jal_warp_num})
);
VX_generic_register #(.N(34 + `NW_M1 + 1)) branch_reg(
.clk (clk),
.reset(reset),
.stall(zero),
.flush(zero),
.in ({VX_branch_rsp_temp.valid_branch, VX_branch_rsp_temp.branch_dir, VX_branch_rsp_temp.branch_warp_num, VX_branch_rsp_temp.branch_dest}),
.out ({VX_branch_rsp.valid_branch , VX_branch_rsp.branch_dir , VX_branch_rsp.branch_warp_num , VX_branch_rsp.branch_dest })
);
// always @(*) begin
// case(in_alu_op)
// `CSR_ALU_RW: out_csr_result = in_csr_mask;
// `CSR_ALU_RS: out_csr_result = in_csr_data | in_csr_mask;
// `CSR_ALU_RC: out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask);
// default: out_csr_result = 32'hdeadbeef;
// endcase
// end
// assign out_is_csr = VX_exec_unit_req.is_csr;
// assign out_csr_address = VX_exec_unit_req.csr_address;
endmodule : VX_execute_unit

105
rtl/VX_fetch.v
View File

@@ -1,105 +0,0 @@
`include "VX_define.v"
module VX_fetch (
input wire clk,
input wire reset,
VX_wstall_inter VX_wstall,
VX_join_inter VX_join,
input wire schedule_delay,
input wire icache_stage_delay,
input wire[`NW_M1:0] icache_stage_wid,
input wire[`NT-1:0] icache_stage_valids,
output wire out_ebreak,
VX_jal_response_inter VX_jal_rsp,
VX_branch_response_inter VX_branch_rsp,
VX_inst_meta_inter fe_inst_meta_fi,
VX_warp_ctl_inter VX_warp_ctl
);
wire[`NT_M1:0] thread_mask;
wire[`NW_M1:0] warp_num;
wire[31:0] warp_pc;
wire scheduled_warp;
wire pipe_stall;
// Only reason this is there is because there is a hidden assumption that decode is exactly after fetch
// Locals
assign pipe_stall = schedule_delay || icache_stage_delay;
VX_warp_scheduler warp_scheduler(
.clk (clk),
.reset (reset),
.stall (pipe_stall),
.is_barrier (VX_warp_ctl.is_barrier),
.barrier_id (VX_warp_ctl.barrier_id),
.num_warps (VX_warp_ctl.num_warps),
.barrier_warp_num (VX_warp_ctl.warp_num),
// Wspawn
.wspawn (VX_warp_ctl.wspawn),
.wsapwn_pc (VX_warp_ctl.wspawn_pc),
.wspawn_new_active(VX_warp_ctl.wspawn_new_active),
// CTM
.ctm (VX_warp_ctl.change_mask),
.ctm_mask (VX_warp_ctl.thread_mask),
.ctm_warp_num (VX_warp_ctl.warp_num),
// WHALT
.whalt (VX_warp_ctl.ebreak),
.whalt_warp_num (VX_warp_ctl.warp_num),
// Wstall
.wstall (VX_wstall.wstall),
.wstall_warp_num (VX_wstall.warp_num),
// Lock/release Stuff
.icache_stage_valids(icache_stage_valids),
.icache_stage_wid (icache_stage_wid),
// Join
.is_join (VX_join.is_join),
.join_warp_num (VX_join.join_warp_num),
// Split
.is_split (VX_warp_ctl.is_split),
.dont_split (VX_warp_ctl.dont_split),
.split_new_mask (VX_warp_ctl.split_new_mask),
.split_later_mask (VX_warp_ctl.split_later_mask),
.split_save_pc (VX_warp_ctl.split_save_pc),
.split_warp_num (VX_warp_ctl.warp_num),
// JAL
.jal (VX_jal_rsp.jal),
.jal_dest (VX_jal_rsp.jal_dest),
.jal_warp_num (VX_jal_rsp.jal_warp_num),
// Branch
.branch_valid (VX_branch_rsp.valid_branch),
.branch_dir (VX_branch_rsp.branch_dir),
.branch_dest (VX_branch_rsp.branch_dest),
.branch_warp_num (VX_branch_rsp.branch_warp_num),
// Outputs
.thread_mask (thread_mask),
.warp_num (warp_num),
.warp_pc (warp_pc),
.out_ebreak (out_ebreak),
.scheduled_warp (scheduled_warp)
);
assign fe_inst_meta_fi.warp_num = warp_num;
assign fe_inst_meta_fi.valid = thread_mask;
assign fe_inst_meta_fi.instruction = 32'h0;
assign fe_inst_meta_fi.inst_pc = warp_pc;
wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0);
wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0);
endmodule

131
rtl/VX_front_end.v
View File

@@ -1,131 +0,0 @@
`include "VX_define.v"
module VX_front_end (
input wire clk,
input wire reset,
input wire schedule_delay,
VX_warp_ctl_inter VX_warp_ctl,
VX_gpu_dcache_res_inter VX_icache_rsp,
VX_gpu_dcache_req_inter VX_icache_req,
VX_jal_response_inter VX_jal_rsp,
VX_branch_response_inter VX_branch_rsp,
VX_frE_to_bckE_req_inter VX_bckE_req,
output wire fetch_ebreak
);
VX_inst_meta_inter fe_inst_meta_fi();
VX_inst_meta_inter fe_inst_meta_fi2();
VX_inst_meta_inter fe_inst_meta_id();
VX_frE_to_bckE_req_inter VX_frE_to_bckE_req();
VX_inst_meta_inter fd_inst_meta_de();
wire total_freeze = schedule_delay;
wire icache_stage_delay;
/* verilator lint_off UNUSED */
// wire real_fetch_ebreak;
/* verilator lint_on UNUSED */
wire vortex_ebreak;
wire terminate_sim;
wire[`NW_M1:0] icache_stage_wid;
wire[`NT-1:0] icache_stage_valids;
reg old_ebreak; // This should be eventually removed
always @(posedge clk) begin
if (reset) begin
old_ebreak <= 0;
end else begin
old_ebreak <= old_ebreak || fetch_ebreak;
end
end
assign fetch_ebreak = vortex_ebreak || terminate_sim || old_ebreak;
VX_wstall_inter VX_wstall();
VX_join_inter VX_join();
VX_fetch vx_fetch(
.clk (clk),
.reset (reset),
.icache_stage_wid (icache_stage_wid),
.icache_stage_valids(icache_stage_valids),
.VX_wstall (VX_wstall),
.VX_join (VX_join),
.schedule_delay (schedule_delay),
.VX_jal_rsp (VX_jal_rsp),
.VX_warp_ctl (VX_warp_ctl),
.icache_stage_delay (icache_stage_delay),
.VX_branch_rsp (VX_branch_rsp),
.out_ebreak (vortex_ebreak), // fetch_ebreak
.fe_inst_meta_fi (fe_inst_meta_fi)
);
wire freeze_fi_reg = total_freeze || icache_stage_delay;
VX_f_d_reg vx_f_i_reg(
.clk (clk),
.reset (reset),
.in_freeze (freeze_fi_reg),
.fe_inst_meta_fd(fe_inst_meta_fi),
.fd_inst_meta_de(fe_inst_meta_fi2)
);
VX_icache_stage VX_icache_stage(
.clk (clk),
.reset (reset),
.total_freeze (total_freeze),
.icache_stage_delay (icache_stage_delay),
.icache_stage_valids(icache_stage_valids),
.icache_stage_wid (icache_stage_wid),
.fe_inst_meta_fi (fe_inst_meta_fi2),
.fe_inst_meta_id (fe_inst_meta_id),
.VX_icache_rsp (VX_icache_rsp),
.VX_icache_req (VX_icache_req)
);
VX_i_d_reg vx_i_d_reg(
.clk (clk),
.reset (reset),
.in_freeze (total_freeze),
.fe_inst_meta_fd(fe_inst_meta_id),
.fd_inst_meta_de(fd_inst_meta_de)
);
VX_decode vx_decode(
.fd_inst_meta_de (fd_inst_meta_de),
.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
.VX_wstall (VX_wstall),
.VX_join (VX_join),
.terminate_sim (terminate_sim)
);
wire no_br_stall = 0;
VX_d_e_reg vx_d_e_reg(
.clk (clk),
.reset (reset),
.in_branch_stall(no_br_stall),
.in_freeze (total_freeze),
.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
.VX_bckE_req (VX_bckE_req)
);
endmodule

32
rtl/VX_generic_priority_encoder.v
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@@ -1,32 +0,0 @@
`ifndef VX_GENERIC_PRIORITY_ENCODER
`define VX_GENERIC_PRIORITY_ENCODER
`include "VX_define.v"
module VX_generic_priority_encoder
#(
parameter N = 1
)
(
input wire[N-1:0] valids,
//output reg[$clog2(N)-1:0] index,
output reg[(`CLOG2(N))-1:0] index,
//output reg[`CLOG2(N):0] index, // eh
output reg found
);
integer i;
always @(*) begin
index = 0;
found = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
//index = i[$clog2(N)-1:0];
index = i[(`CLOG2(N))-1:0];
found = 1;
end
end
end
endmodule
`endif

49
rtl/VX_generic_queue.v
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@@ -1,49 +0,0 @@
module VX_generic_queue
#(
parameter DATAW = 4,
parameter SIZE = 277
)
(
input wire clk,
input wire reset,
input wire push,
input wire[DATAW-1:0] in_data,
input wire pop,
output wire[DATAW-1:0] out_data,
output wire empty,
output wire full
);
reg[DATAW-1:0] data[SIZE-1:0];
reg[$clog2(SIZE)-1:0] head;
reg[$clog2(SIZE)-1:0] tail;
assign empty = head == tail;
assign full = head == (tail+1);
integer i;
always @(posedge clk) begin
if (reset) begin
head <= 0;
tail <= 0;
for (i = 0; i < SIZE; i=i+1) begin
data[i] <= 0;
end
end else begin
if (push && !full) begin
data[tail] <= in_data;
tail <= tail+1;
end
if (pop && !empty) begin
head <= head + 1;
end
end
end
assign out_data = data[head];
endmodule

143
rtl/VX_generic_queue_ll.v
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@@ -1,143 +0,0 @@
`include "VX_define_synth.v"
module VX_generic_queue_ll
#(
parameter DATAW = 4,
parameter SIZE = 277
)
(
input wire clk,
input wire reset,
input wire push,
input wire [DATAW-1:0] in_data,
input wire pop,
output wire [DATAW-1:0] out_data,
output wire empty,
output wire full
);
/* verilator lint_off WIDTH */
if (SIZE == 0) begin
assign empty = 1;
assign out_data = 0;
assign full = 0;
end else begin // (SIZE > 0)
`ifdef QUEUE_FORCE_MLAB
(* syn_ramstyle = "mlab" *) reg[DATAW-1:0] data[SIZE-1:0];
`else
reg[ DATAW-1:0] data[SIZE-1:0];
`endif
reg [DATAW-1:0] head_r;
reg [$clog2(SIZE+1)-1:0] size_r;
wire reading;
wire writing;
assign reading = pop && !empty;
assign writing = push && !full;
if (SIZE == 1) begin
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
head_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= 1;
end else if (reading && !writing) begin
size_r <= 0;
end
if (writing) begin
head_r <= in_data;
end
end
end
assign out_data = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0) && !pop;
end else begin // (SIZE > 1)
reg [DATAW-1:0] curr_r;
reg [$clog2(SIZE)-1:0] wr_ctr_r;
reg [$clog2(SIZE)-1:0] rd_ptr_r;
reg [$clog2(SIZE)-1:0] rd_next_ptr_r;
reg empty_r;
reg full_r;
reg bypass_r;
always @(posedge clk) begin
if (reset) begin
wr_ctr_r <= 0;
end else begin
if (writing)
wr_ctr_r <= wr_ctr_r + 1;
end
end
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
empty_r <= 1;
full_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= size_r + 1;
empty_r <= 0;
if (size_r == SIZE-1)
full_r <= 1;
end else if (reading && !writing) begin
size_r <= size_r - 1;
if (size_r == 1)
empty_r <= 1;
full_r <= 0;
end
end
end
always @(posedge clk) begin
if (writing) begin
data[wr_ctr_r] <= in_data;
end
end
always @(posedge clk) begin
if (reset) begin
curr_r <= 0;
rd_ptr_r <= 0;
rd_next_ptr_r <= 1;
bypass_r <= 0;
end else begin
if (reading) begin
if (SIZE == 2) begin
rd_ptr_r <= rd_next_ptr_r;
rd_next_ptr_r <= ~rd_next_ptr_r;
end else if (SIZE > 2) begin
rd_ptr_r <= rd_next_ptr_r;
rd_next_ptr_r <= rd_ptr_r + 2;
end
end
bypass_r <= writing && (empty_r || (1 == size_r) && reading);
curr_r <= in_data;
head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r];
end
end
assign out_data = bypass_r ? curr_r : head_r;
assign empty = empty_r;
assign full = full_r;
end
end
/* verilator lint_on WIDTH */
endmodule

35
rtl/VX_generic_register.v
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@@ -1,35 +0,0 @@
module VX_generic_register
#( parameter N = 1, parameter Valid = 1)
(
input wire clk,
input wire reset,
input wire stall,
input wire flush,
input wire[(N-1):0] in,
output wire[(N-1):0] out
);
if (Valid == 0) begin
assign out = in;
end else begin
reg[(N-1):0] value;
always @(posedge clk or posedge reset) begin
if (reset) begin
value <= 0;
end else if (flush) begin
value <= 0;
end else if (~stall) begin
value <= in;
end
end
assign out = value;
end
endmodule

39
rtl/VX_generic_stack.v
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@@ -1,39 +0,0 @@
module VX_generic_stack
#(
parameter WIDTH = 40,
parameter DEPTH = 2
)
(
input wire clk,
input wire reset,
input wire push,
input wire pop,
input reg [WIDTH - 1:0] q1,
input reg [WIDTH - 1:0] q2,
output wire[WIDTH - 1:0] d
);
reg [DEPTH - 1:0] ptr;
reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
integer i;
always @(posedge clk) begin
if (reset) begin
ptr <= 0;
for (i = 0; i < (1 << DEPTH); i=i+1) stack[i] <= 0;
end else if (push) begin
stack[ptr] <= q1;
stack[ptr+1] <= q2;
ptr <= ptr + 2;
end else if (pop) begin
ptr <= ptr - 1;
end
end
assign d = stack[ptr - 1];
endmodule

91
rtl/VX_gpgpu_inst.v
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@@ -1,91 +0,0 @@
`include "VX_define.v"
module VX_gpgpu_inst (
// Input
VX_gpu_inst_req_inter VX_gpu_inst_req,
// Output
VX_warp_ctl_inter VX_warp_ctl
);
wire[`NT_M1:0] curr_valids = VX_gpu_inst_req.valid;
wire is_split = (VX_gpu_inst_req.is_split);
wire[`NT_M1:0] tmc_new_mask;
wire all_threads = `NT < VX_gpu_inst_req.a_reg_data[0];
genvar curr_t;
generate
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin : tmc_new_mask_init
assign tmc_new_mask[curr_t] = all_threads ? 1 : curr_t < VX_gpu_inst_req.a_reg_data[0];
end
endgenerate
wire valid_inst = (|curr_valids);
assign VX_warp_ctl.warp_num = VX_gpu_inst_req.warp_num;
assign VX_warp_ctl.change_mask = (VX_gpu_inst_req.is_tmc) && valid_inst;
assign VX_warp_ctl.thread_mask = VX_gpu_inst_req.is_tmc ? tmc_new_mask : 0;
// assign VX_warp_ctl.ebreak = (VX_gpu_inst_req.a_reg_data[0] == 0) && valid_inst;
assign VX_warp_ctl.ebreak = VX_warp_ctl.change_mask && (VX_warp_ctl.thread_mask == 0);
wire wspawn = VX_gpu_inst_req.is_wspawn;
wire[31:0] wspawn_pc = VX_gpu_inst_req.rd2;
wire all_active = `NW < VX_gpu_inst_req.a_reg_data[0];
wire[`NW-1:0] wspawn_new_active;
genvar curr_w;
generate
for (curr_w = 0; curr_w < `NW; curr_w=curr_w+1) begin : wspawn_new_active_init
assign wspawn_new_active[curr_w] = all_active ? 1 : curr_w < VX_gpu_inst_req.a_reg_data[0];
end
endgenerate
assign VX_warp_ctl.is_barrier = VX_gpu_inst_req.is_barrier && valid_inst;
assign VX_warp_ctl.barrier_id = VX_gpu_inst_req.a_reg_data[0];
wire[31:0] num_warps_m1 = VX_gpu_inst_req.rd2 - 1;
assign VX_warp_ctl.num_warps = num_warps_m1[$clog2(`NW):0];
assign VX_warp_ctl.wspawn = wspawn;
assign VX_warp_ctl.wspawn_pc = wspawn_pc;
assign VX_warp_ctl.wspawn_new_active = wspawn_new_active;
wire[`NT_M1:0] split_new_use_mask;
wire[`NT_M1:0] split_new_later_mask;
// VX_gpu_inst_req.pc
genvar curr_s_t;
generate
for (curr_s_t = 0; curr_s_t < `NT; curr_s_t=curr_s_t+1) begin : masks_init
wire curr_bool = (VX_gpu_inst_req.a_reg_data[curr_s_t] == 32'b1);
assign split_new_use_mask[curr_s_t] = curr_valids[curr_s_t] & (curr_bool);
assign split_new_later_mask[curr_s_t] = curr_valids[curr_s_t] & (!curr_bool);
end
endgenerate
wire[$clog2(`NT):0] num_valids;
VX_countones #(.N(`NT)) valids_counter (
.valids(curr_valids),
.count (num_valids)
);
// wire[`NW_M1:0] num_valids = $countones(curr_valids);
assign VX_warp_ctl.is_split = is_split && (num_valids > 1);
assign VX_warp_ctl.dont_split = VX_warp_ctl.is_split && ((split_new_use_mask == 0) || (split_new_use_mask == {`NT{1'b1}}));
assign VX_warp_ctl.split_new_mask = split_new_use_mask;
assign VX_warp_ctl.split_later_mask = split_new_later_mask;
assign VX_warp_ctl.split_save_pc = VX_gpu_inst_req.pc_next;
assign VX_warp_ctl.split_warp_num = VX_gpu_inst_req.warp_num;
// VX_gpu_inst_req.is_wspawn
// VX_gpu_inst_req.is_split
// VX_gpu_inst_req.is_barrier
endmodule

172
rtl/VX_gpr.v
View File

@@ -1,172 +0,0 @@
`include "VX_define.v"
module VX_gpr (
input wire clk,
input wire reset,
input wire valid_write_request,
VX_gpr_read_inter VX_gpr_read,
VX_wb_inter VX_writeback_inter,
output reg[`NT_M1:0][31:0] out_a_reg_data,
output reg[`NT_M1:0][31:0] out_b_reg_data
);
wire write_enable;
`ifndef ASIC
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0)) && (VX_writeback_inter.rd != 0);
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.reset (reset),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data),
.q2 (out_b_reg_data)
);
`else
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0));
wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid);
wire[`NT_M1:0][31:0] write_bit_mask;
genvar curr_t;
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin
wire local_write = write_enable & VX_writeback_inter.wb_valid[curr_t];
assign write_bit_mask[curr_t] = {32{~local_write}};
end
// wire cenb = !going_to_write;
wire cenb = 0;
// wire cena_1 = (VX_gpr_read.rs1 == 0);
// wire cena_2 = (VX_gpr_read.rs2 == 0);
wire cena_1 = 0;
wire cena_2 = 0;
wire[`NT_M1:0][31:0] temp_a;
wire[`NT_M1:0][31:0] temp_b;
`ifndef SYN
genvar thread;
genvar curr_bit;
for (thread = 0; thread < `NT; thread = thread + 1)
begin
for (curr_bit = 0; curr_bit < 32; curr_bit=curr_bit+1)
begin
assign out_a_reg_data[thread][curr_bit] = ((temp_a[thread][curr_bit] === 1'dx) || cena_1 )? 1'b0 : temp_a[thread][curr_bit];
assign out_b_reg_data[thread][curr_bit] = ((temp_b[thread][curr_bit] === 1'dx) || cena_2) ? 1'b0 : temp_b[thread][curr_bit];
end
end
`else
assign out_a_reg_data = temp_a;
assign out_b_reg_data = temp_b;
`endif
wire[`NT_M1:0][31:0] to_write = (VX_writeback_inter.rd != 0) ? VX_writeback_inter.write_data : 0;
genvar curr_base_thread;
for (curr_base_thread = 0; curr_base_thread < 'NT; curr_base_thread=curr_base_thread+4)
begin
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 first_ram (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(temp_a[(curr_base_thread+3):(curr_base_thread)]),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena_1),
.AA(VX_gpr_read.rs1[(curr_base_thread+3):(curr_base_thread)]),
.CLKB(clk),
.CENB(cenb),
.WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]),
.AB(VX_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]),
.DB(to_write[(curr_base_thread+3):(curr_base_thread)]),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(5'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 second_ram (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(temp_b[(curr_base_thread+3):(curr_base_thread)]),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena_2),
.AA(VX_gpr_read.rs2[(curr_base_thread+3):(curr_base_thread)]),
.CLKB(clk),
.CENB(cenb),
.WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]),
.AB(VX_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]),
.DB(to_write[(curr_base_thread+3):(curr_base_thread)]),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(5'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
end
`endif
endmodule

228
rtl/VX_gpr_stage.v
View File

@@ -1,228 +0,0 @@
`include "VX_define.v"
module VX_gpr_stage (
input wire clk,
input wire reset,
input wire schedule_delay,
input wire memory_delay,
input wire exec_delay,
input wire stall_gpr_csr,
output wire gpr_stage_delay,
// inputs
// Instruction Information
VX_frE_to_bckE_req_inter VX_bckE_req,
// WriteBack inputs
VX_wb_inter VX_writeback_inter,
// Outputs
VX_exec_unit_req_inter VX_exec_unit_req,
VX_lsu_req_inter VX_lsu_req,
VX_gpu_inst_req_inter VX_gpu_inst_req,
VX_csr_req_inter VX_csr_req
);
wire[31:0] curr_PC = VX_bckE_req.curr_PC;
wire[2:0] branchType = VX_bckE_req.branch_type;
wire is_store = (VX_bckE_req.mem_write != `NO_MEM_WRITE);
wire is_load = (VX_bckE_req.mem_read != `NO_MEM_READ);
wire jalQual = VX_bckE_req.jalQual;
VX_gpr_read_inter VX_gpr_read();
assign VX_gpr_read.rs1 = VX_bckE_req.rs1;
assign VX_gpr_read.rs2 = VX_bckE_req.rs2;
assign VX_gpr_read.warp_num = VX_bckE_req.warp_num;
`ifndef ASIC
VX_gpr_jal_inter VX_gpr_jal();
assign VX_gpr_jal.is_jal = VX_bckE_req.jalQual;
assign VX_gpr_jal.curr_PC = VX_bckE_req.curr_PC;
`else
VX_gpr_jal_inter VX_gpr_jal();
assign VX_gpr_jal.is_jal = VX_exec_unit_req.jalQual;
assign VX_gpr_jal.curr_PC = VX_exec_unit_req.curr_PC;
`endif
VX_gpr_data_inter VX_gpr_datf();
VX_gpr_wrapper vx_grp_wrapper(
.clk (clk),
.reset (reset),
.VX_writeback_inter(VX_writeback_inter),
.VX_gpr_read (VX_gpr_read),
.VX_gpr_jal (VX_gpr_jal),
.out_a_reg_data (VX_gpr_datf.a_reg_data),
.out_b_reg_data (VX_gpr_datf.b_reg_data)
);
// assign VX_bckE_req.is_csr = is_csr;
// assign VX_bckE_req_out.csr_mask = (VX_bckE_req.sr_immed == 1'b1) ? {27'h0, VX_bckE_req.rs1} : VX_gpr_data.a_reg_data[0];
// Outputs
VX_exec_unit_req_inter VX_exec_unit_req_temp();
VX_lsu_req_inter VX_lsu_req_temp();
VX_gpu_inst_req_inter VX_gpu_inst_req_temp();
VX_csr_req_inter VX_csr_req_temp();
VX_inst_multiplex VX_inst_mult(
.VX_bckE_req (VX_bckE_req),
.VX_gpr_data (VX_gpr_datf),
.VX_exec_unit_req(VX_exec_unit_req_temp),
.VX_lsu_req (VX_lsu_req_temp),
.VX_gpu_inst_req (VX_gpu_inst_req_temp),
.VX_csr_req (VX_csr_req_temp)
);
wire is_lsu = (|VX_lsu_req_temp.valid);
wire stall_rest = 0;
wire flush_rest = schedule_delay;
wire stall_lsu = memory_delay;
wire flush_lsu = schedule_delay && !stall_lsu;
wire stall_exec = exec_delay;
wire flush_exec = schedule_delay && !stall_exec;
wire stall_csr = stall_gpr_csr && VX_bckE_req.is_csr && (|VX_bckE_req.valid);
assign gpr_stage_delay = stall_lsu || stall_exec || stall_csr;
`ifdef ASIC
wire delayed_lsu_last_cycle;
VX_generic_register #(.N(1)) delayed_reg (
.clk (clk),
.reset(reset),
.stall(stall_rest),
.flush(stall_rest),
.in (stall_lsu),
.out (delayed_lsu_last_cycle)
);
wire[`NT_M1:0][31:0] temp_store_data;
wire[`NT_M1:0][31:0] temp_base_address; // A reg data
wire[`NT_M1:0][31:0] real_store_data;
wire[`NT_M1:0][31:0] real_base_address; // A reg data
wire store_curr_real = !delayed_lsu_last_cycle && stall_lsu;
VX_generic_register #(.N(`NT*32*2)) lsu_data(
.clk (clk),
.reset(reset),
.stall(!store_curr_real),
.flush(stall_rest),
.in ({real_store_data, real_base_address}),
.out ({temp_store_data, temp_base_address})
);
assign real_store_data = VX_lsu_req_temp.store_data;
assign real_base_address = VX_lsu_req_temp.base_address;
assign VX_lsu_req.store_data = (delayed_lsu_last_cycle) ? temp_store_data : real_store_data;
assign VX_lsu_req.base_address = (delayed_lsu_last_cycle) ? temp_base_address : real_base_address;
VX_generic_register #(.N(77 + `NW_M1 + 1 + (`NT))) lsu_reg(
.clk (clk),
.reset(reset),
.stall(stall_lsu),
.flush(flush_lsu),
.in ({VX_lsu_req_temp.valid, VX_lsu_req_temp.lsu_pc, VX_lsu_req_temp.warp_num, VX_lsu_req_temp.offset, VX_lsu_req_temp.mem_read, VX_lsu_req_temp.mem_write, VX_lsu_req_temp.rd, VX_lsu_req_temp.wb}),
.out ({VX_lsu_req.valid , VX_lsu_req.lsu_pc ,VX_lsu_req.warp_num , VX_lsu_req.offset , VX_lsu_req.mem_read , VX_lsu_req.mem_write , VX_lsu_req.rd , VX_lsu_req.wb })
);
VX_generic_register #(.N(224 + `NW_M1 + 1 + (`NT))) exec_unit_reg(
.clk (clk),
.reset(reset),
.stall(stall_exec),
.flush(flush_exec),
.in ({VX_exec_unit_req_temp.valid, VX_exec_unit_req_temp.warp_num, VX_exec_unit_req_temp.curr_PC, VX_exec_unit_req_temp.PC_next, VX_exec_unit_req_temp.rd, VX_exec_unit_req_temp.wb, VX_exec_unit_req_temp.alu_op, VX_exec_unit_req_temp.rs1, VX_exec_unit_req_temp.rs2, VX_exec_unit_req_temp.rs2_src, VX_exec_unit_req_temp.itype_immed, VX_exec_unit_req_temp.upper_immed, VX_exec_unit_req_temp.branch_type, VX_exec_unit_req_temp.jalQual, VX_exec_unit_req_temp.jal, VX_exec_unit_req_temp.jal_offset, VX_exec_unit_req_temp.ebreak, VX_exec_unit_req_temp.wspawn, VX_exec_unit_req_temp.is_csr, VX_exec_unit_req_temp.csr_address, VX_exec_unit_req_temp.csr_immed, VX_exec_unit_req_temp.csr_mask}),
.out ({VX_exec_unit_req.valid , VX_exec_unit_req.warp_num , VX_exec_unit_req.curr_PC , VX_exec_unit_req.PC_next , VX_exec_unit_req.rd , VX_exec_unit_req.wb , VX_exec_unit_req.alu_op , VX_exec_unit_req.rs1 , VX_exec_unit_req.rs2 , VX_exec_unit_req.rs2_src , VX_exec_unit_req.itype_immed , VX_exec_unit_req.upper_immed , VX_exec_unit_req.branch_type , VX_exec_unit_req.jalQual , VX_exec_unit_req.jal , VX_exec_unit_req.jal_offset , VX_exec_unit_req.ebreak , VX_exec_unit_req.wspawn , VX_exec_unit_req.is_csr , VX_exec_unit_req.csr_address , VX_exec_unit_req.csr_immed , VX_exec_unit_req.csr_mask })
);
assign VX_exec_unit_req.a_reg_data = real_base_address;
assign VX_exec_unit_req.b_reg_data = real_store_data;
VX_generic_register #(.N(36 + `NW_M1 + 1 + (`NT))) gpu_inst_reg(
.clk (clk),
.reset(reset),
.stall(stall_rest),
.flush(flush_rest),
.in ({VX_gpu_inst_req_temp.valid, VX_gpu_inst_req_temp.warp_num, VX_gpu_inst_req_temp.is_wspawn, VX_gpu_inst_req_temp.is_tmc, VX_gpu_inst_req_temp.is_split, VX_gpu_inst_req_temp.is_barrier, VX_gpu_inst_req_temp.pc_next}),
.out ({VX_gpu_inst_req.valid , VX_gpu_inst_req.warp_num , VX_gpu_inst_req.is_wspawn , VX_gpu_inst_req.is_tmc , VX_gpu_inst_req.is_split , VX_gpu_inst_req.is_barrier , VX_gpu_inst_req.pc_next })
);
assign VX_gpu_inst_req.a_reg_data = real_base_address;
assign VX_gpu_inst_req.rd2 = real_store_data;
VX_generic_register #(.N(`NW_M1 + 1 + `NT + 58)) csr_reg(
.clk (clk),
.reset(reset),
.stall(stall_gpr_csr),
.flush(flush_rest),
.in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.alu_op, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}),
.out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.alu_op , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask })
);
// assign
`else
// 341
VX_generic_register #(.N(77 + `NW_M1 + 1 + 65*(`NT))) lsu_reg(
.clk (clk),
.reset(reset),
.stall(stall_lsu),
.flush(flush_lsu),
.in ({VX_lsu_req_temp.valid, VX_lsu_req_temp.lsu_pc, VX_lsu_req_temp.warp_num, VX_lsu_req_temp.store_data, VX_lsu_req_temp.base_address, VX_lsu_req_temp.offset, VX_lsu_req_temp.mem_read, VX_lsu_req_temp.mem_write, VX_lsu_req_temp.rd, VX_lsu_req_temp.wb}),
.out ({VX_lsu_req.valid , VX_lsu_req.lsu_pc , VX_lsu_req.warp_num , VX_lsu_req.store_data , VX_lsu_req.base_address , VX_lsu_req.offset , VX_lsu_req.mem_read , VX_lsu_req.mem_write , VX_lsu_req.rd , VX_lsu_req.wb })
);
VX_generic_register #(.N(224 + `NW_M1 + 1 + 65*(`NT))) exec_unit_reg(
.clk (clk),
.reset(reset),
.stall(stall_exec),
.flush(flush_exec),
.in ({VX_exec_unit_req_temp.valid, VX_exec_unit_req_temp.warp_num, VX_exec_unit_req_temp.curr_PC, VX_exec_unit_req_temp.PC_next, VX_exec_unit_req_temp.rd, VX_exec_unit_req_temp.wb, VX_exec_unit_req_temp.a_reg_data, VX_exec_unit_req_temp.b_reg_data, VX_exec_unit_req_temp.alu_op, VX_exec_unit_req_temp.rs1, VX_exec_unit_req_temp.rs2, VX_exec_unit_req_temp.rs2_src, VX_exec_unit_req_temp.itype_immed, VX_exec_unit_req_temp.upper_immed, VX_exec_unit_req_temp.branch_type, VX_exec_unit_req_temp.jalQual, VX_exec_unit_req_temp.jal, VX_exec_unit_req_temp.jal_offset, VX_exec_unit_req_temp.ebreak, VX_exec_unit_req_temp.wspawn, VX_exec_unit_req_temp.is_csr, VX_exec_unit_req_temp.csr_address, VX_exec_unit_req_temp.csr_immed, VX_exec_unit_req_temp.csr_mask}),
.out ({VX_exec_unit_req.valid , VX_exec_unit_req.warp_num , VX_exec_unit_req.curr_PC , VX_exec_unit_req.PC_next , VX_exec_unit_req.rd , VX_exec_unit_req.wb , VX_exec_unit_req.a_reg_data , VX_exec_unit_req.b_reg_data , VX_exec_unit_req.alu_op , VX_exec_unit_req.rs1 , VX_exec_unit_req.rs2 , VX_exec_unit_req.rs2_src , VX_exec_unit_req.itype_immed , VX_exec_unit_req.upper_immed , VX_exec_unit_req.branch_type , VX_exec_unit_req.jalQual , VX_exec_unit_req.jal , VX_exec_unit_req.jal_offset , VX_exec_unit_req.ebreak , VX_exec_unit_req.wspawn , VX_exec_unit_req.is_csr , VX_exec_unit_req.csr_address , VX_exec_unit_req.csr_immed , VX_exec_unit_req.csr_mask })
);
VX_generic_register #(.N(68 + `NW_M1 + 1 + 33*(`NT))) gpu_inst_reg(
.clk (clk),
.reset(reset),
.stall(stall_rest),
.flush(flush_rest),
.in ({VX_gpu_inst_req_temp.valid, VX_gpu_inst_req_temp.warp_num, VX_gpu_inst_req_temp.is_wspawn, VX_gpu_inst_req_temp.is_tmc, VX_gpu_inst_req_temp.is_split, VX_gpu_inst_req_temp.is_barrier, VX_gpu_inst_req_temp.pc_next, VX_gpu_inst_req_temp.a_reg_data, VX_gpu_inst_req_temp.rd2}),
.out ({VX_gpu_inst_req.valid , VX_gpu_inst_req.warp_num , VX_gpu_inst_req.is_wspawn , VX_gpu_inst_req.is_tmc , VX_gpu_inst_req.is_split , VX_gpu_inst_req.is_barrier , VX_gpu_inst_req.pc_next , VX_gpu_inst_req.a_reg_data , VX_gpu_inst_req.rd2 })
);
VX_generic_register #(.N(`NW_M1 + 1 + `NT + 58)) csr_reg(
.clk (clk),
.reset(reset),
.stall(stall_gpr_csr),
.flush(flush_rest),
.in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.alu_op, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}),
.out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.alu_op , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask })
);
`endif
endmodule : VX_gpr_stage

72
rtl/VX_gpr_wrapper.v
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@@ -1,72 +0,0 @@
`include "VX_define.v"
module VX_gpr_wrapper (
input wire clk,
input wire reset,
VX_gpr_read_inter VX_gpr_read,
VX_wb_inter VX_writeback_inter,
VX_gpr_jal_inter VX_gpr_jal,
output wire[`NT_M1:0][31:0] out_a_reg_data,
output wire[`NT_M1:0][31:0] out_b_reg_data
);
wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data;
wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data;
wire[`NT_M1:0][31:0] jal_data;
genvar index;
generate
for (index = 0; index <= `NT_M1; index = index + 1) begin : jal_data_assign
assign jal_data[index] = VX_gpr_jal.curr_PC;
end
endgenerate
`ifndef ASIC
assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[VX_gpr_read.warp_num]));
assign out_b_reg_data = (temp_b_reg_data[VX_gpr_read.warp_num]);
`else
wire zer = 0;
wire[`NW_M1:0] old_warp_num;
VX_generic_register #(`NW_M1+1) store_wn(
.clk (clk),
.reset(reset),
.stall(zer),
.flush(zer),
.in (VX_gpr_read.warp_num),
.out (old_warp_num)
);
assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[old_warp_num]));
assign out_b_reg_data = (temp_b_reg_data[old_warp_num]);
`endif
genvar warp_index;
generate
for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin : warp_gprs
wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
VX_gpr vx_gpr(
.clk (clk),
.reset (reset),
.valid_write_request(valid_write_request),
.VX_gpr_read (VX_gpr_read),
.VX_writeback_inter (VX_writeback_inter),
.out_a_reg_data (temp_a_reg_data[warp_index]),
.out_b_reg_data (temp_b_reg_data[warp_index])
);
end
endgenerate
endmodule

65
rtl/VX_icache_stage.v
View File

@@ -1,65 +0,0 @@
`include "VX_define.v"
module VX_icache_stage (
input wire clk,
input wire reset,
input wire total_freeze,
output wire icache_stage_delay,
output wire[`NW_M1:0] icache_stage_wid,
output wire[`NT-1:0] icache_stage_valids,
VX_inst_meta_inter fe_inst_meta_fi,
VX_inst_meta_inter fe_inst_meta_id,
VX_gpu_dcache_res_inter VX_icache_rsp,
VX_gpu_dcache_req_inter VX_icache_req
);
reg[`NT-1:0] threads_active[`NW-1:0];
wire valid_inst = (|fe_inst_meta_fi.valid);
// Icache Request
assign VX_icache_req.core_req_valid = valid_inst && !total_freeze;
assign VX_icache_req.core_req_addr = fe_inst_meta_fi.inst_pc;
assign VX_icache_req.core_req_writedata = 32'b0;
assign VX_icache_req.core_req_mem_read = `LW_MEM_READ;
assign VX_icache_req.core_req_mem_write = `NO_MEM_WRITE;
assign VX_icache_req.core_req_rd = 5'b0;
assign VX_icache_req.core_req_wb = {1{2'b1}};
assign VX_icache_req.core_req_warp_num = fe_inst_meta_fi.warp_num;
assign VX_icache_req.core_req_pc = fe_inst_meta_fi.inst_pc;
assign fe_inst_meta_id.instruction = VX_icache_rsp.core_wb_readdata[0][31:0];
assign fe_inst_meta_id.inst_pc = VX_icache_rsp.core_wb_pc[0];
assign fe_inst_meta_id.warp_num = VX_icache_rsp.core_wb_warp_num;
/* verilator lint_off WIDTH */
assign fe_inst_meta_id.valid = VX_icache_rsp.core_wb_valid ? threads_active[VX_icache_rsp.core_wb_warp_num] : 0;
/* verilator lint_off WIDTH */
assign icache_stage_wid = fe_inst_meta_id.warp_num;
assign icache_stage_valids = fe_inst_meta_id.valid & {`NT{!icache_stage_delay}};
// Cache can't accept request
assign icache_stage_delay = VX_icache_rsp.delay_req;
// Core can't accept response
assign VX_icache_req.core_no_wb_slot = total_freeze;
integer curr_w;
always @(posedge clk) begin
if (reset) begin
for (curr_w = 0; curr_w < `NW; curr_w=curr_w+1) threads_active[curr_w] <= 0;
end else begin
if (valid_inst && !icache_stage_delay) begin
/* verilator lint_off WIDTH */
threads_active[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid;
/* verilator lint_on WIDTH */
end
end
end
endmodule

97
rtl/VX_inst_multiplex.v
View File

@@ -1,97 +0,0 @@
`include "VX_define.v"
module VX_inst_multiplex (
// Inputs
VX_frE_to_bckE_req_inter VX_bckE_req,
VX_gpr_data_inter VX_gpr_data,
// Outputs
VX_exec_unit_req_inter VX_exec_unit_req,
VX_lsu_req_inter VX_lsu_req,
VX_gpu_inst_req_inter VX_gpu_inst_req,
VX_csr_req_inter VX_csr_req
);
wire[`NT_M1:0] is_mem_mask;
wire[`NT_M1:0] is_gpu_mask;
wire[`NT_M1:0] is_csr_mask;
wire is_mem = (VX_bckE_req.mem_write != `NO_MEM_WRITE) || (VX_bckE_req.mem_read != `NO_MEM_READ);
wire is_gpu = (VX_bckE_req.is_wspawn || VX_bckE_req.is_tmc || VX_bckE_req.is_barrier || VX_bckE_req.is_split);
wire is_csr = VX_bckE_req.is_csr;
// wire is_gpu = 0;
genvar currT;
generate
for (currT = 0; currT < `NT; currT = currT + 1) begin : mask_init
assign is_mem_mask[currT] = is_mem;
assign is_gpu_mask[currT] = is_gpu;
assign is_csr_mask[currT] = is_csr;
end
endgenerate
// LSU Unit
assign VX_lsu_req.valid = VX_bckE_req.valid & is_mem_mask;
assign VX_lsu_req.warp_num = VX_bckE_req.warp_num;
assign VX_lsu_req.base_address = VX_gpr_data.a_reg_data;
assign VX_lsu_req.store_data = VX_gpr_data.b_reg_data;
assign VX_lsu_req.offset = VX_bckE_req.itype_immed;
assign VX_lsu_req.mem_read = VX_bckE_req.mem_read;
assign VX_lsu_req.mem_write = VX_bckE_req.mem_write;
assign VX_lsu_req.rd = VX_bckE_req.rd;
assign VX_lsu_req.wb = VX_bckE_req.wb;
assign VX_lsu_req.lsu_pc = VX_bckE_req.curr_PC;
// Execute Unit
assign VX_exec_unit_req.valid = VX_bckE_req.valid & (~is_mem_mask & ~is_gpu_mask & ~is_csr_mask);
assign VX_exec_unit_req.warp_num = VX_bckE_req.warp_num;
assign VX_exec_unit_req.curr_PC = VX_bckE_req.curr_PC;
assign VX_exec_unit_req.PC_next = VX_bckE_req.PC_next;
assign VX_exec_unit_req.rd = VX_bckE_req.rd;
assign VX_exec_unit_req.wb = VX_bckE_req.wb;
assign VX_exec_unit_req.a_reg_data = VX_gpr_data.a_reg_data;
assign VX_exec_unit_req.b_reg_data = VX_gpr_data.b_reg_data;
assign VX_exec_unit_req.alu_op = VX_bckE_req.alu_op;
assign VX_exec_unit_req.rs1 = VX_bckE_req.rs1;
assign VX_exec_unit_req.rs2 = VX_bckE_req.rs2;
assign VX_exec_unit_req.rs2_src = VX_bckE_req.rs2_src;
assign VX_exec_unit_req.itype_immed = VX_bckE_req.itype_immed;
assign VX_exec_unit_req.upper_immed = VX_bckE_req.upper_immed;
assign VX_exec_unit_req.branch_type = VX_bckE_req.branch_type;
assign VX_exec_unit_req.jalQual = VX_bckE_req.jalQual;
assign VX_exec_unit_req.jal = VX_bckE_req.jal;
assign VX_exec_unit_req.jal_offset = VX_bckE_req.jal_offset;
assign VX_exec_unit_req.ebreak = VX_bckE_req.ebreak;
// GPR Req
assign VX_gpu_inst_req.valid = VX_bckE_req.valid & is_gpu_mask;
assign VX_gpu_inst_req.warp_num = VX_bckE_req.warp_num;
assign VX_gpu_inst_req.is_wspawn = VX_bckE_req.is_wspawn;
assign VX_gpu_inst_req.is_tmc = VX_bckE_req.is_tmc;
assign VX_gpu_inst_req.is_split = VX_bckE_req.is_split;
assign VX_gpu_inst_req.is_barrier = VX_bckE_req.is_barrier;
assign VX_gpu_inst_req.a_reg_data = VX_gpr_data.a_reg_data;
assign VX_gpu_inst_req.rd2 = VX_gpr_data.b_reg_data[0];
assign VX_gpu_inst_req.pc_next = VX_bckE_req.PC_next;
// CSR Req
assign VX_csr_req.valid = VX_bckE_req.valid & is_csr_mask;
assign VX_csr_req.warp_num = VX_bckE_req.warp_num;
assign VX_csr_req.rd = VX_bckE_req.rd;
assign VX_csr_req.wb = VX_bckE_req.wb;
assign VX_csr_req.alu_op = VX_bckE_req.alu_op;
assign VX_csr_req.is_csr = VX_bckE_req.is_csr;
assign VX_csr_req.csr_address = VX_bckE_req.csr_address;
assign VX_csr_req.csr_immed = VX_bckE_req.csr_immed;
assign VX_csr_req.csr_mask = VX_bckE_req.csr_mask;
endmodule

90
rtl/VX_lsu.v
View File

@@ -1,90 +0,0 @@
`include "VX_define.v"
module VX_lsu (
input wire clk,
input wire reset,
input wire no_slot_mem,
VX_lsu_req_inter VX_lsu_req,
// Write back to GPR
VX_inst_mem_wb_inter VX_mem_wb,
VX_gpu_dcache_res_inter VX_dcache_rsp,
VX_gpu_dcache_req_inter VX_dcache_req,
output wire out_delay
);
// Generate Addresses
wire[`NT_M1:0][31:0] address;
VX_lsu_addr_gen VX_lsu_addr_gen
(
.base_address(VX_lsu_req.base_address),
.offset (VX_lsu_req.offset),
.address (address)
);
wire[`NT_M1:0][31:0] use_address;
wire[`NT_M1:0][31:0] use_store_data;
wire[`NT_M1:0] use_valid;
wire[2:0] use_mem_read;
wire[2:0] use_mem_write;
wire[4:0] use_rd;
wire[`NW_M1:0] use_warp_num;
wire[1:0] use_wb;
wire[31:0] use_pc;
wire zero = 0;
VX_generic_register #(.N(45 + `NW_M1 + 1 + `NT*65)) lsu_buffer(
.clk (clk),
.reset(reset),
.stall(out_delay),
.flush(zero),
.in ({address , VX_lsu_req.store_data, VX_lsu_req.valid, VX_lsu_req.mem_read, VX_lsu_req.mem_write, VX_lsu_req.rd, VX_lsu_req.warp_num, VX_lsu_req.wb, VX_lsu_req.lsu_pc}),
.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
);
// Core Request
assign VX_dcache_req.core_req_valid = use_valid;
assign VX_dcache_req.core_req_addr = use_address;
assign VX_dcache_req.core_req_writedata = use_store_data;
assign VX_dcache_req.core_req_mem_read = {`NT{use_mem_read}};
assign VX_dcache_req.core_req_mem_write = {`NT{use_mem_write}};
assign VX_dcache_req.core_req_rd = use_rd;
assign VX_dcache_req.core_req_wb = {`NT{use_wb}};
assign VX_dcache_req.core_req_warp_num = use_warp_num;
assign VX_dcache_req.core_req_pc = use_pc;
// Core can't accept response
assign VX_dcache_req.core_no_wb_slot = no_slot_mem;
// Cache can't accept request
assign out_delay = VX_dcache_rsp.delay_req;
// Core Response
assign VX_mem_wb.rd = VX_dcache_rsp.core_wb_req_rd;
assign VX_mem_wb.wb = VX_dcache_rsp.core_wb_req_wb;
assign VX_mem_wb.wb_valid = VX_dcache_rsp.core_wb_valid;
assign VX_mem_wb.wb_warp_num = VX_dcache_rsp.core_wb_warp_num;
assign VX_mem_wb.loaded_data = VX_dcache_rsp.core_wb_readdata;
wire[(`CLOG2(`NT))-1:0] use_pc_index;
wire found;
VX_generic_priority_encoder #(.N(`NT)) pick_first_pc(
.valids(VX_dcache_rsp.core_wb_valid),
.index (use_pc_index),
.found (found)
);
assign VX_mem_wb.mem_wb_pc = VX_dcache_rsp.core_wb_pc[use_pc_index];
endmodule // Memory

18
rtl/VX_lsu_addr_gen.v
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@@ -1,18 +0,0 @@
`include "VX_define.v"
module VX_lsu_addr_gen (
input wire[`NT_M1:0][31:0] base_address,
input wire[31:0] offset,
output wire[`NT_M1:0][31:0] address
);
genvar index;
generate
for (index = 0; index < `NT; index = index + 1) begin : addresses
assign address[index] = base_address[index] + offset;
end
endgenerate
endmodule

20
rtl/VX_priority_encoder.v
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@@ -1,20 +0,0 @@
`include "VX_define.v"
module VX_priority_encoder (
input wire[`NW-1:0] valids,
output reg[`NW_M1:0] index,
output reg found
);
integer i;
always @(*) begin
index = 0;
found = 0;
for (i = `NW-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
index = i[`NW_M1:0];
found = 1;
end
end
end
endmodule

32
rtl/VX_priority_encoder_w_mask.v
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@@ -1,32 +0,0 @@
`include "VX_define.v"
module VX_priority_encoder_w_mask
#(
parameter N = 10
)
(
input wire[N-1:0] valids,
output reg [N-1:0] mask,
//output reg[$clog2(N)-1:0] index,
output reg[(`CLOG2(N))-1:0] index,
//output reg[`CLOG2(N):0] index, // eh
output reg found
);
integer i;
always @(valids) begin
index = 0;
found = 0;
// mask = 0;
for (i = 0; i < N; i=i+1) begin
if (valids[i]) begin
//index = i[$clog2(N)-1:0];
index = i[(`CLOG2(N))-1:0];
found = 1;
// mask[index] = (1 << i);
// $display("%h",(1 << i));
end
end
end
assign mask = found ? (1 << index) : 0;
endmodule

83
rtl/VX_scheduler.v
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@@ -1,83 +0,0 @@
`include "VX_define.v"
module VX_scheduler (
input wire clk,
input wire reset,
input wire memory_delay,
input wire exec_delay,
input wire gpr_stage_delay,
VX_frE_to_bckE_req_inter VX_bckE_req,
VX_wb_inter VX_writeback_inter,
output wire schedule_delay,
output wire is_empty
);
/* verilator lint_off WIDTH */
reg[31:0] count_valid;
assign is_empty = count_valid == 0;
reg[31:0][`NT-1:0] rename_table[`NW-1:0];
wire valid_wb = (VX_writeback_inter.wb != 0) && (|VX_writeback_inter.wb_valid) && (VX_writeback_inter.rd != 0);
wire wb_inc = (VX_bckE_req.wb != 0) && (VX_bckE_req.rd != 0);
wire rs1_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs1] != 0;
wire rs2_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rs2] != 0;
wire rd_rename = rename_table[VX_bckE_req.warp_num][VX_bckE_req.rd ] != 0;
wire is_store = (VX_bckE_req.mem_write != `NO_MEM_WRITE);
wire is_load = (VX_bckE_req.mem_read != `NO_MEM_READ);
// classify our next instruction.
wire is_mem = is_store || is_load;
wire is_gpu = (VX_bckE_req.is_wspawn || VX_bckE_req.is_tmc || VX_bckE_req.is_barrier || VX_bckE_req.is_split);
wire is_csr = VX_bckE_req.is_csr;
wire is_exec = !is_mem && !is_gpu && !is_csr;
// wire rs1_pass = 0;
// wire rs2_pass = 0;
wire using_rs2 = (VX_bckE_req.rs2_src == `RS2_REG) || is_store || VX_bckE_req.is_barrier || VX_bckE_req.is_wspawn;
wire rs1_rename_qual = ((rs1_rename) && (VX_bckE_req.rs1 != 0));
wire rs2_rename_qual = ((rs2_rename) && (VX_bckE_req.rs2 != 0 && using_rs2));
wire rd_rename_qual = ((rd_rename ) && (VX_bckE_req.rd != 0));
wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual;
assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid))
|| (memory_delay && is_mem)
|| (gpr_stage_delay && (is_mem || is_exec))
|| (exec_delay && is_exec);
integer i;
integer w;
always @(posedge clk or posedge reset) begin
if (reset) begin
for (w = 0; w < `NW; w=w+1)
begin
for (i = 0; i < 32; i = i + 1)
begin
rename_table[w][i] <= 0;
end
end
end else begin
if (valid_wb ) rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] <= rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] & (~VX_writeback_inter.wb_valid);
if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.warp_num ][VX_bckE_req.rd ] <= VX_bckE_req.valid;
if (valid_wb && ((rename_table[VX_writeback_inter.wb_warp_num][VX_writeback_inter.rd] & (~VX_writeback_inter.wb_valid)) == 0)) count_valid = count_valid - 1;
if (!schedule_delay && wb_inc) count_valid = count_valid + 1;
end
end
/* verilator lint_on WIDTH */
endmodule

87
rtl/VX_warp.v
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@@ -1,87 +0,0 @@
`include "VX_define.v"
module VX_warp (
input wire clk,
input wire reset,
input wire stall,
input wire remove,
input wire[`NT_M1:0] in_thread_mask,
input wire in_change_mask,
input wire in_jal,
input wire[31:0] in_jal_dest,
input wire in_branch_dir,
input wire[31:0] in_branch_dest,
input wire in_wspawn,
input wire[31:0] in_wspawn_pc,
output wire[31:0] out_PC,
output wire[`NT_M1:0] out_valid
);
reg[31:0] real_PC;
logic [31:0] temp_PC;
logic [31:0] use_PC;
reg[`NT_M1:0] valid;
reg[`NT_M1:0] valid_zero;
integer ini_cur_th = 0;
initial begin
real_PC = 0;
for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1) begin
valid[ini_cur_th] = 0; // Thread 1 active
valid_zero[ini_cur_th] = 0;
end
valid[0] = 1;
valid_zero[0] = 0;
end
always @(posedge clk, posedge reset) begin
if (remove) begin
valid <= valid_zero;
end else if (in_change_mask) begin
valid <= in_thread_mask;
end
end
genvar out_cur_th;
generate
for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1) begin : out_valid_assign
assign out_valid[out_cur_th] = in_change_mask ? in_thread_mask[out_cur_th] : stall ? 1'b0 : valid[out_cur_th];
end
endgenerate
always @(*) begin
if (in_jal == 1'b1) begin
temp_PC = in_jal_dest;
// $display("LINKING TO %h", temp_PC);
end else if (in_branch_dir == 1'b1) begin
temp_PC = in_branch_dest;
end else begin
temp_PC = real_PC;
end
end
assign use_PC = temp_PC;
assign out_PC = temp_PC;
always @(posedge clk or posedge reset) begin
if (reset) begin
real_PC <= 0;
end else if (in_wspawn == 1'b1) begin
// $display("Inside warp ***** Spawn @ %H",in_wspawn_pc);
real_PC <= in_wspawn_pc;
end else if (!stall) begin
real_PC <= use_PC + 32'h4;
end else begin
real_PC <= use_PC;
end
end
endmodule

343
rtl/VX_warp_scheduler.v
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@@ -1,343 +0,0 @@
`include "VX_define.v"
module VX_warp_scheduler (
input wire clk, // Clock
input wire reset,
input wire stall,
// Wspawn
input wire wspawn,
input wire[31:0] wsapwn_pc,
input wire[`NW-1:0] wspawn_new_active,
// CTM
input wire ctm,
input wire[`NT_M1:0] ctm_mask,
input wire[`NW_M1:0] ctm_warp_num,
// WHALT
input wire whalt,
input wire[`NW_M1:0] whalt_warp_num,
input wire is_barrier,
input wire[31:0] barrier_id,
input wire[$clog2(`NW):0] num_warps,
input wire[`NW_M1:0] barrier_warp_num,
// WSTALL
input wire wstall,
input wire[`NW_M1:0] wstall_warp_num,
// Split
input wire is_split,
input wire dont_split,
input wire[`NT_M1:0] split_new_mask,
input wire[`NT_M1:0] split_later_mask,
input wire[31:0] split_save_pc,
input wire[`NW_M1:0] split_warp_num,
// Join
input wire is_join,
input wire[`NW_M1:0] join_warp_num,
// JAL
input wire jal,
input wire[31:0] jal_dest,
input wire[`NW_M1:0] jal_warp_num,
// Branch
input wire branch_valid,
input wire branch_dir,
input wire[31:0] branch_dest,
input wire[`NW_M1:0] branch_warp_num,
output wire[`NT_M1:0] thread_mask,
output wire[`NW_M1:0] warp_num,
output wire[31:0] warp_pc,
output wire out_ebreak,
output wire scheduled_warp,
input wire[`NW_M1:0] icache_stage_wid,
input wire[`NT-1:0] icache_stage_valids
);
/* verilator lint_off WIDTH */
wire update_use_wspawn;
wire update_visible_active;
wire[(1+32+`NT_M1):0] d[`NW-1:0];
wire join_fall;
wire[31:0] join_pc;
wire[`NT_M1:0] join_tm;
wire in_wspawn = wspawn;
wire in_ctm = ctm;
wire in_whalt = whalt;
wire in_wstall = wstall;
reg[`NW-1:0] warp_active;
reg[`NW-1:0] warp_stalled;
reg [`NW-1:0] visible_active;
wire[`NW-1:0] use_active;
reg [`NW-1:0] warp_lock;
wire wstall_this_cycle;
reg[`NT_M1:0] thread_masks[`NW-1:0];
reg[31:0] warp_pcs[`NW-1:0];
// barriers
reg[`NW-1:0] barrier_stall_mask[(`NUM_BARRIERS-1):0];
wire reached_barrier_limit;
wire[`NW-1:0] curr_barrier_mask;
wire[$clog2(`NW):0] curr_barrier_count;
// wsapwn
reg[31:0] use_wsapwn_pc;
reg[`NW-1:0] use_wsapwn;
wire[`NW_M1:0] warp_to_schedule;
wire schedule;
wire hazard;
wire global_stall;
wire real_schedule;
wire[31:0] new_pc;
reg[`NW-1:0] total_barrier_stall;
reg didnt_split;
/* verilator lint_off UNUSED */
// wire[$clog2(`NW):0] num_active;
/* verilator lint_on UNUSED */
integer curr_w_help;
integer curr_barrier;
always @(posedge clk or posedge reset) begin
if (reset) begin
for (curr_barrier = 0; curr_barrier < `NUM_BARRIERS; curr_barrier=curr_barrier+1) begin
barrier_stall_mask[curr_barrier] <= 0;
end
use_wsapwn_pc <= 0;
use_wsapwn <= 0;
warp_pcs[0] <= (32'h80000000 - 4);
warp_active[0] <= 1; // Activating first warp
visible_active[0] <= 1; // Activating first warp
thread_masks[0] <= 1; // Activating first thread in first warp
warp_stalled <= 0;
didnt_split <= 0;
warp_lock <= 0;
// total_barrier_stall = 0;
for (curr_w_help = 1; curr_w_help < `NW; curr_w_help=curr_w_help+1) begin
warp_pcs[curr_w_help] <= 0;
warp_active[curr_w_help] <= 0; // Activating first warp
visible_active[curr_w_help] <= 0; // Activating first warp
thread_masks[curr_w_help] <= 1; // Activating first thread in first warp
end
end else begin
// Wsapwning warps
if (wspawn) begin
warp_active <= wspawn_new_active;
use_wsapwn_pc <= wsapwn_pc;
use_wsapwn <= wspawn_new_active & (~`NW'b1);
end
if (is_barrier) begin
warp_stalled[barrier_warp_num] <= 0;
if (reached_barrier_limit) begin
barrier_stall_mask[barrier_id] <= 0;
end else begin
barrier_stall_mask[barrier_id][barrier_warp_num] <= 1;
end
end else if (ctm) begin
thread_masks[ctm_warp_num] <= ctm_mask;
warp_stalled[ctm_warp_num] <= 0;
end else if (is_join && !didnt_split) begin
if (!join_fall) begin
warp_pcs[join_warp_num] <= join_pc;
end
thread_masks[join_warp_num] <= join_tm;
didnt_split <= 0;
end else if (is_split) begin
warp_stalled[split_warp_num] <= 0;
if (!dont_split) begin
thread_masks[split_warp_num] <= split_new_mask;
didnt_split <= 0;
end else begin
didnt_split <= 1;
end
end
if (whalt) begin
warp_active[whalt_warp_num] <= 0;
visible_active[whalt_warp_num] <= 0;
end
if (update_use_wspawn) begin
use_wsapwn[warp_to_schedule] <= 0;
thread_masks[warp_to_schedule] <= 1;
end
// Stalling the scheduling of warps
if (wstall) begin
warp_stalled[wstall_warp_num] <= 1;
visible_active[wstall_warp_num] <= 0;
end
// Refilling active warps
if (update_visible_active) begin
visible_active <= warp_active & (~warp_stalled) & (~total_barrier_stall) & ~warp_lock;
end
// Don't change state if stall
if (!global_stall && real_schedule && (thread_mask != 0)) begin
visible_active[warp_to_schedule] <= 0;
warp_pcs[warp_to_schedule] <= new_pc;
end
// Jal
if (jal) begin
warp_pcs[jal_warp_num] <= jal_dest;
warp_stalled[jal_warp_num] <= 0;
end
// Branch
if (branch_valid) begin
if (branch_dir) warp_pcs[branch_warp_num] <= branch_dest;
warp_stalled[branch_warp_num] <= 0;
end
// Lock/Release
if (scheduled_warp && !stall) begin
warp_lock[warp_num] <= 1'b1;
// warp_lock <= {`NW{1'b1}};
end
if (|icache_stage_valids && !stall) begin
warp_lock[icache_stage_wid] <= 1'b0;
// warp_lock <= {`NW{1'b0}};
end
end
end
VX_countones #(.N(`NW)) barrier_count(
.valids(curr_barrier_mask),
.count (curr_barrier_count)
);
wire[$clog2(`NW):0] count_visible_active;
VX_countones #(.N(`NW)) num_visible(
.valids(visible_active),
.count (count_visible_active)
);
// assign curr_barrier_count = $countones(curr_barrier_mask);
assign curr_barrier_mask = barrier_stall_mask[barrier_id][`NW-1:0];
assign reached_barrier_limit = curr_barrier_count == (num_warps);
assign wstall_this_cycle = wstall && (wstall_warp_num == warp_to_schedule); // Maybe bug
assign total_barrier_stall = barrier_stall_mask[0] | barrier_stall_mask[1] | barrier_stall_mask[2] | barrier_stall_mask[3];
// integer curr_b;
// always @(*) begin
// total_barrier_stall = 0;
// for (curr_b = 0; curr_b < `NUM_BARRIERS; curr_b=curr_b+1)
// begin
// total_barrier_stall[`NW-1:0] = total_barrier_stall[`NW-1:0] | barrier_stall_mask[curr_b];
// end
// end
assign update_visible_active = (count_visible_active < 1) && !(stall || wstall_this_cycle || hazard || is_join);
wire[(1+32+`NT_M1):0] q1 = {1'b1, 32'b0 , thread_masks[split_warp_num]};
wire[(1+32+`NT_M1):0] q2 = {1'b0, split_save_pc , split_later_mask};
assign {join_fall, join_pc, join_tm} = d[join_warp_num];
genvar curr_warp;
generate
for (curr_warp = 0; curr_warp < `NW; curr_warp = curr_warp + 1) begin : stacks
wire correct_warp_s = (curr_warp == split_warp_num);
wire correct_warp_j = (curr_warp == join_warp_num);
wire push = (is_split && !dont_split) && correct_warp_s;
wire pop = is_join && correct_warp_j;
VX_generic_stack #(.WIDTH(1+32+`NT), .DEPTH($clog2(`NT)+1)) ipdom_stack(
.clk (clk),
.reset(reset),
.push (push),
.pop (pop),
.d (d[curr_warp]),
.q1 (q1),
.q2 (q2)
);
end
endgenerate
// wire should_stall = stall || (jal && (warp_to_schedule == jal_warp_num)) || (branch_dir && (warp_to_schedule == branch_warp_num));
wire should_jal = (jal && (warp_to_schedule == jal_warp_num));
wire should_bra = (branch_dir && (warp_to_schedule == branch_warp_num));
assign hazard = (should_jal || should_bra) && schedule;
assign real_schedule = schedule && !warp_stalled[warp_to_schedule] && !total_barrier_stall[warp_to_schedule] && !warp_lock[0];
assign global_stall = (stall || wstall_this_cycle || hazard || !real_schedule || is_join);
assign scheduled_warp = !(wstall_this_cycle || hazard || !real_schedule || is_join) && !reset;
wire real_use_wspawn = use_wsapwn[warp_to_schedule];
assign warp_pc = real_use_wspawn ? use_wsapwn_pc : warp_pcs[warp_to_schedule];
assign thread_mask = (global_stall) ? 0 : (real_use_wspawn ? `NT'b1 : thread_masks[warp_to_schedule]);
assign warp_num = warp_to_schedule;
assign update_use_wspawn = use_wsapwn[warp_to_schedule] && !global_stall;
assign new_pc = warp_pc + 4;
assign use_active = (count_visible_active < 1) ? (warp_active & (~warp_stalled) & (~total_barrier_stall) & (~warp_lock)) : visible_active;
// Choosing a warp to schedule
VX_priority_encoder choose_schedule(
.valids(use_active),
.index (warp_to_schedule),
.found (schedule)
);
// always @(*) begin
// $display("WarpPC: %h",warp_pc);
// $display("real_schedule: %d, schedule: %d, warp_stalled: %d, warp_to_schedule: %d, total_barrier_stall: %d",real_schedule, schedule, warp_stalled[warp_to_schedule], warp_to_schedule, total_barrier_stall[warp_to_schedule]);
// end
// Valid counter
// assign num_active = $countones(visible_active);
// VX_one_counter valid_counter(
// .valids(visible_active),
// .ones_found()
// );
wire ebreak = (warp_active == 0);
assign out_ebreak = ebreak;
/* verilator lint_on WIDTH */
endmodule

95
rtl/VX_writeback.v
View File

@@ -1,95 +0,0 @@
`include "VX_define.v"
module VX_writeback (
input wire clk,
input wire reset,
// Mem WB info
VX_inst_mem_wb_inter VX_mem_wb,
// EXEC Unit WB info
VX_inst_exec_wb_inter VX_inst_exec_wb,
// CSR Unit WB info
VX_csr_wb_inter VX_csr_wb,
// Actual WB to GPR
VX_wb_inter VX_writeback_inter,
output wire no_slot_mem,
output wire no_slot_exec,
output wire no_slot_csr
);
VX_wb_inter VX_writeback_tempp();
wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid);
wire mem_wb = (VX_mem_wb.wb != 0) && (|VX_mem_wb.wb_valid);
wire csr_wb = (VX_csr_wb.wb != 0) && (|VX_csr_wb.valid);
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
assign no_slot_csr = csr_wb && (exec_wb);
assign no_slot_exec = 0;
assign VX_writeback_tempp.write_data = exec_wb ? VX_inst_exec_wb.alu_result :
csr_wb ? VX_csr_wb.csr_result :
mem_wb ? VX_mem_wb.loaded_data :
0;
assign VX_writeback_tempp.wb_valid = exec_wb ? VX_inst_exec_wb.wb_valid :
csr_wb ? VX_csr_wb.valid :
mem_wb ? VX_mem_wb.wb_valid :
0;
assign VX_writeback_tempp.rd = exec_wb ? VX_inst_exec_wb.rd :
csr_wb ? VX_csr_wb.rd :
mem_wb ? VX_mem_wb.rd :
0;
assign VX_writeback_tempp.wb = exec_wb ? VX_inst_exec_wb.wb :
csr_wb ? VX_csr_wb.wb :
mem_wb ? VX_mem_wb.wb :
0;
assign VX_writeback_tempp.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num :
csr_wb ? VX_csr_wb.warp_num :
mem_wb ? VX_mem_wb.wb_warp_num :
0;
assign VX_writeback_tempp.wb_pc = exec_wb ? VX_inst_exec_wb.exec_wb_pc :
csr_wb ? 32'hdeadbeef :
mem_wb ? VX_mem_wb.mem_wb_pc :
32'hdeadbeef;
wire zero = 0;
wire[`NT-1:0][31:0] use_wb_data;
VX_generic_register #(.N(39 + `NW_M1 + 1 + `NT*33)) wb_register(
.clk (clk),
.reset(reset),
.stall(zero),
.flush(zero),
.in ({VX_writeback_tempp.write_data, VX_writeback_tempp.wb_valid, VX_writeback_tempp.rd, VX_writeback_tempp.wb, VX_writeback_tempp.wb_warp_num, VX_writeback_tempp.wb_pc}),
.out ({use_wb_data , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc})
);
reg[31:0] last_data_wb /* verilator public */ ;
always @(posedge clk) begin
if ((|VX_writeback_inter.wb_valid) && (VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd == 28)) begin
last_data_wb <= use_wb_data[0];
end
end
assign VX_writeback_inter.write_data = use_wb_data;
endmodule : VX_writeback

310
rtl/Vortex.v
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@@ -1,310 +0,0 @@
`include "VX_define.v"
`include "VX_cache_config.v"
module Vortex
#(
parameter CORE_ID = 0
) (
`ifdef SINGLE_CORE_BENCH
// Clock
input wire clk,
input wire reset,
// IO
output wire io_valid,
output wire[31:0] io_data,
// DRAM Dcache Req
output wire dram_req,
output wire dram_req_write,
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG],
output wire [31:0] dram_expected_lat,
input wire dram_req_delay,
// DRAM Dcache Res
output wire dram_fill_accept,
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
// DRAM Icache Req
output wire I_dram_req,
output wire I_dram_req_write,
output wire I_dram_req_read,
output wire [31:0] I_dram_req_addr,
output wire [31:0] I_dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
output wire [31:0] I_dram_expected_lat,
// DRAM Icache Res
output wire I_dram_fill_accept,
input wire I_dram_fill_rsp,
input wire [31:0] I_dram_fill_rsp_addr,
input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
// LLC Snooping
input wire snp_req,
input wire [31:0] snp_req_addr,
output wire snp_req_delay,
input wire I_snp_req,
input wire [31:0] I_snp_req_addr,
output wire I_snp_req_delay,
output wire out_ebreak
`else
input wire clk,
input wire reset,
// IO
output wire io_valid,
output wire[31:0] io_data,
// DRAM Dcache Req
output wire dram_req,
output wire dram_req_write,
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire [31:0] dram_expected_lat,
// DRAM Dcache Res
output wire dram_fill_accept,
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
// DRAM Icache Req
output wire I_dram_req,
output wire I_dram_req_write,
output wire I_dram_req_read,
output wire [31:0] I_dram_req_addr,
output wire [31:0] I_dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
output wire [31:0] I_dram_expected_lat,
// DRAM Icache Res
output wire I_dram_fill_accept,
input wire I_dram_fill_rsp,
input wire [31:0] I_dram_fill_rsp_addr,
input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
input wire dram_req_delay,
input wire snp_req,
input wire [31:0] snp_req_addr,
output wire snp_req_delay,
input wire I_snp_req,
input wire [31:0] I_snp_req_addr,
output wire I_snp_req_delay,
output wire out_ebreak
`endif
);
wire scheduler_empty;
wire out_ebreak_unqual;
// assign out_ebreak = out_ebreak_unqual && (scheduler_empty && 1);
assign out_ebreak = out_ebreak_unqual;
wire memory_delay;
wire exec_delay;
wire gpr_stage_delay;
wire schedule_delay;
// Dcache Interface
VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp();
VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req();
VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_qual();
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_req();
VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_res();
assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp;
assign VX_gpu_dcache_dram_res.dram_fill_rsp_addr = dram_fill_rsp_addr;
assign dram_req = VX_gpu_dcache_dram_req.dram_req;
assign dram_req_write = VX_gpu_dcache_dram_req.dram_req_write;
assign dram_req_read = VX_gpu_dcache_dram_req.dram_req_read;
assign dram_req_addr = VX_gpu_dcache_dram_req.dram_req_addr;
assign dram_req_size = VX_gpu_dcache_dram_req.dram_req_size;
assign dram_expected_lat = `DSIMULATED_DRAM_LATENCY_CYCLES;
assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept;
assign VX_gpu_dcache_dram_req.dram_req_delay = dram_req_delay;
genvar wordy;
generate
for (wordy = 0; wordy < `DBANK_LINE_SIZE_WORDS; wordy=wordy+1) begin
assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[wordy] = dram_fill_rsp_data[wordy];
assign dram_req_data[wordy] = VX_gpu_dcache_dram_req.dram_req_data[wordy];
end
endgenerate
wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write[0] != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000);
wire[31:0] temp_io_data = VX_dcache_req.core_req_writedata[0];
assign io_valid = temp_io_valid;
assign io_data = temp_io_data;
assign VX_dcache_req_qual.core_req_valid = VX_dcache_req.core_req_valid & {`NT{~io_valid}};
assign VX_dcache_req_qual.core_req_addr = VX_dcache_req.core_req_addr;
assign VX_dcache_req_qual.core_req_writedata = VX_dcache_req.core_req_writedata;
assign VX_dcache_req_qual.core_req_mem_read = VX_dcache_req.core_req_mem_read;
assign VX_dcache_req_qual.core_req_mem_write = VX_dcache_req.core_req_mem_write;
assign VX_dcache_req_qual.core_req_rd = VX_dcache_req.core_req_rd;
assign VX_dcache_req_qual.core_req_wb = VX_dcache_req.core_req_wb;
assign VX_dcache_req_qual.core_req_warp_num = VX_dcache_req.core_req_warp_num;
assign VX_dcache_req_qual.core_req_pc = VX_dcache_req.core_req_pc;
assign VX_dcache_req_qual.core_no_wb_slot = VX_dcache_req.core_no_wb_slot;
VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`INUMBER_REQUESTS)) VX_icache_rsp();
VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`INUMBER_REQUESTS)) VX_icache_req();
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`IBANK_LINE_SIZE_WORDS)) VX_gpu_icache_dram_req();
VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`IBANK_LINE_SIZE_WORDS)) VX_gpu_icache_dram_res();
assign VX_gpu_icache_dram_res.dram_fill_rsp = I_dram_fill_rsp;
assign VX_gpu_icache_dram_res.dram_fill_rsp_addr = I_dram_fill_rsp_addr;
assign I_dram_req = VX_gpu_icache_dram_req.dram_req;
assign I_dram_req_write = VX_gpu_icache_dram_req.dram_req_write;
assign I_dram_req_read = VX_gpu_icache_dram_req.dram_req_read;
assign I_dram_req_addr = VX_gpu_icache_dram_req.dram_req_addr;
assign I_dram_req_size = VX_gpu_icache_dram_req.dram_req_size;
assign I_dram_expected_lat = `ISIMULATED_DRAM_LATENCY_CYCLES;
assign I_dram_fill_accept = VX_gpu_icache_dram_req.dram_fill_accept;
assign VX_gpu_icache_dram_req.dram_req_delay = dram_req_delay;
genvar iwordy;
generate
for (iwordy = 0; iwordy < `IBANK_LINE_SIZE_WORDS; iwordy=iwordy+1) begin
assign VX_gpu_icache_dram_res.dram_fill_rsp_data[iwordy] = I_dram_fill_rsp_data[iwordy];
assign I_dram_req_data[iwordy] = VX_gpu_icache_dram_req.dram_req_data[iwordy];
end
endgenerate
/////////////////////////////////////////////////////////////////////////
// Front-end to Back-end
VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM
// Back-end to Front-end
VX_wb_inter VX_writeback_inter(); // Writeback to GPRs
VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch
VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch
// CSR Buses
// VX_csr_write_request_inter VX_csr_w_req();
VX_warp_ctl_inter VX_warp_ctl();
VX_gpu_snp_req_rsp VX_gpu_icache_snp_req();
VX_gpu_snp_req_rsp VX_gpu_dcache_snp_req();
assign VX_gpu_icache_snp_req.snp_req = I_snp_req;
assign VX_gpu_icache_snp_req.snp_req_addr = I_snp_req_addr;
assign I_snp_req_delay = VX_gpu_icache_snp_req.snp_delay;
assign VX_gpu_dcache_snp_req.snp_req = snp_req;
assign VX_gpu_dcache_snp_req.snp_req_addr = snp_req_addr;
assign snp_req_delay = VX_gpu_dcache_snp_req.snp_delay;
VX_front_end vx_front_end(
.clk (clk),
.reset (reset),
.VX_warp_ctl (VX_warp_ctl),
.VX_bckE_req (VX_bckE_req),
.schedule_delay (schedule_delay),
.VX_icache_rsp (VX_icache_rsp),
.VX_icache_req (VX_icache_req),
.VX_jal_rsp (VX_jal_rsp),
.VX_branch_rsp (VX_branch_rsp),
.fetch_ebreak (out_ebreak_unqual)
);
VX_scheduler schedule(
.clk (clk),
.reset (reset),
.memory_delay (memory_delay),
.exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay),
.VX_bckE_req (VX_bckE_req),
.VX_writeback_inter(VX_writeback_inter),
.schedule_delay (schedule_delay),
.is_empty (scheduler_empty)
);
VX_back_end #(.CORE_ID(CORE_ID)) vx_back_end(
.clk (clk),
.reset (reset),
.schedule_delay (schedule_delay),
.VX_warp_ctl (VX_warp_ctl),
.VX_bckE_req (VX_bckE_req),
.VX_jal_rsp (VX_jal_rsp),
.VX_branch_rsp (VX_branch_rsp),
.VX_dcache_rsp (VX_dcache_rsp),
.VX_dcache_req (VX_dcache_req),
.VX_writeback_inter (VX_writeback_inter),
.out_mem_delay (memory_delay),
.out_exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay)
);
VX_dmem_controller VX_dmem_controller(
.clk (clk),
.reset (reset),
// Dram <-> Dcache
.VX_gpu_dcache_dram_req (VX_gpu_dcache_dram_req),
.VX_gpu_dcache_dram_res (VX_gpu_dcache_dram_res),
.VX_gpu_dcache_snp_req (VX_gpu_dcache_snp_req),
// Dram <-> Icache
.VX_gpu_icache_dram_req (VX_gpu_icache_dram_req),
.VX_gpu_icache_dram_res (VX_gpu_icache_dram_res),
.VX_gpu_icache_snp_req (VX_gpu_icache_snp_req),
// Core <-> Icache
.VX_icache_req (VX_icache_req),
.VX_icache_rsp (VX_icache_rsp),
// Core <-> Dcache
.VX_dcache_req (VX_dcache_req_qual),
.VX_dcache_rsp (VX_dcache_rsp)
);
// VX_csr_handler vx_csr_handler(
// .clk (clk),
// .in_decode_csr_address(decode_csr_address),
// .VX_csr_w_req (VX_csr_w_req),
// .in_wb_valid (VX_writeback_inter.wb_valid[0]),
// .out_decode_csr_data (csr_decode_csr_data)
// );
endmodule // Vortex

302
rtl/Vortex_Cluster.v
View File

@@ -1,302 +0,0 @@
`include "VX_define.v"
`include "VX_cache_config.v"
module Vortex_Cluster
#(
parameter CLUSTER_ID = 0
)
(
// Clock
input wire clk,
input wire reset,
// IO
output wire[`NUMBER_CORES_PER_CLUSTER-1:0] io_valid,
output wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] io_data,
// DRAM Req
output wire out_dram_req,
output wire out_dram_req_write,
output wire out_dram_req_read,
output wire [31:0] out_dram_req_addr,
output wire [31:0] out_dram_req_size,
output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG],
output wire [31:0] out_dram_expected_lat,
input wire out_dram_req_delay,
// DRAM Res
output wire out_dram_fill_accept,
input wire out_dram_fill_rsp,
input wire [31:0] out_dram_fill_rsp_addr,
input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
// LLC Snooping
input wire llc_snp_req,
input wire[31:0] llc_snp_req_addr,
output wire llc_snp_req_delay,
output wire out_ebreak
);
// DRAM Dcache Req
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_write;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_read;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_size;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_req_data;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_expected_lat;
// DRAM Dcache Res
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_fill_accept;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_fill_rsp;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_fill_rsp_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_fill_rsp_data;
// DRAM Icache Req
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_write;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_read;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_size;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_req_data;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_expected_lat;
// DRAM Icache Res
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_accept;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_rsp;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data;
// Out ebreak
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_out_ebreak;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_io_valid;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_io_data;
wire l2c_core_accept;
wire snp_fwd;
wire[31:0] snp_fwd_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] snp_fwd_delay;
assign out_ebreak = (&per_core_out_ebreak);
genvar curr_core;
generate
for (curr_core = 0; curr_core < `NUMBER_CORES_PER_CLUSTER; curr_core=curr_core+1) begin
wire [`IBANK_LINE_SIZE_RNG][31:0] curr_core_I_dram_req_data;
wire [`DBANK_LINE_SIZE_RNG][31:0] curr_core_dram_req_data ;
assign io_valid[curr_core] = per_core_io_valid[curr_core];
assign io_data [curr_core] = per_core_io_data [curr_core];
Vortex #(.CORE_ID(curr_core + (CLUSTER_ID * `NUMBER_CORES_PER_CLUSTER))) vortex_core(
.clk (clk),
.reset (reset),
.io_valid (per_core_io_valid [curr_core]),
.io_data (per_core_io_data [curr_core]),
.dram_req (per_core_dram_req [curr_core]),
.dram_req_write (per_core_dram_req_write [curr_core]),
.dram_req_read (per_core_dram_req_read [curr_core]),
.dram_req_addr (per_core_dram_req_addr [curr_core]),
.dram_req_size (per_core_dram_req_size [curr_core]),
.dram_req_data (curr_core_dram_req_data ),
.dram_expected_lat (per_core_dram_expected_lat [curr_core]),
.dram_fill_accept (per_core_dram_fill_accept [curr_core]),
.dram_fill_rsp (per_core_dram_fill_rsp [curr_core]),
.dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]),
.dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]),
.I_dram_req (per_core_I_dram_req [curr_core]),
.I_dram_req_write (per_core_I_dram_req_write [curr_core]),
.I_dram_req_read (per_core_I_dram_req_read [curr_core]),
.I_dram_req_addr (per_core_I_dram_req_addr [curr_core]),
.I_dram_req_size (per_core_I_dram_req_size [curr_core]),
.I_dram_req_data (curr_core_I_dram_req_data ),
.I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]),
.I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]),
.I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]),
.I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]),
.I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]),
.dram_req_delay (l2c_core_accept ),
.out_ebreak (per_core_out_ebreak [curr_core]),
.snp_req (snp_fwd),
.snp_req_addr (snp_fwd_addr),
.snp_req_delay (snp_fwd_delay[curr_core]),
.I_snp_req (0),
.I_snp_req_addr (),
.I_snp_req_delay ()
);
assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data;
assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data;
end
endgenerate
//////////////////// L2 Cache ////////////////////
wire[`LLNUMBER_REQUESTS-1:0] l2c_core_req;
wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write;
wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read;
wire[`LLNUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr;
wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_core_req_data;
wire[`LLNUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb;
wire[`LLNUMBER_REQUESTS-1:0] l2c_core_no_wb_slot;
wire[`LLNUMBER_REQUESTS-1:0] l2c_wb;
wire[`LLNUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr;
wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_wb_data;
wire[`DBANK_LINE_SIZE_RNG][31:0] dram_req_data_port;
wire[`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data_port;
genvar llb_index;
generate
for (llb_index = 0; llb_index < `DBANK_LINE_SIZE_WORDS; llb_index=llb_index+1) begin
assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index];
assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index];
end
endgenerate
//
genvar l2c_curr_core;
generate
for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin
// Core Request
assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)];
assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)];
assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write[(l2c_curr_core/2)] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write
assign l2c_core_req_mem_read [l2c_curr_core] = per_core_dram_req_read[(l2c_curr_core/2)] ? `LW_MEM_READ : `NO_MEM_READ;
assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write
assign l2c_core_req_wb [l2c_curr_core] = per_core_dram_req_read[(l2c_curr_core/2)] ? 1 : 0;
assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write
assign l2c_core_req_addr [l2c_curr_core] = per_core_dram_req_addr [(l2c_curr_core/2)];
assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)];
assign l2c_core_req_data [l2c_curr_core] = per_core_dram_req_data [(l2c_curr_core/2)];
assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)];
// Core can't accept Response
assign l2c_core_no_wb_slot [l2c_curr_core] = ~per_core_dram_fill_accept [(l2c_curr_core/2)];
assign l2c_core_no_wb_slot [l2c_curr_core+1] = ~per_core_I_dram_fill_accept[(l2c_curr_core/2)];
// Cache Fill Response
assign per_core_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core];
assign per_core_I_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1];
assign per_core_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core];
assign per_core_I_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1];
assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core];
assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1];
end
endgenerate
wire dram_snp_full;
wire dram_req_because_of_wb;
VX_cache #(
.CACHE_SIZE_BYTES (`LLCACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (`LLNUMBER_BANKS),
.WORD_SIZE_BYTES (`LLWORD_SIZE_BYTES),
.NUMBER_REQUESTS (`LLNUMBER_REQUESTS),
.STAGE_1_CYCLES (`LLSTAGE_1_CYCLES),
.FUNC_ID (`LLFUNC_ID),
.REQQ_SIZE (`LLREQQ_SIZE),
.MRVQ_SIZE (`LLMRVQ_SIZE),
.DFPQ_SIZE (`LLDFPQ_SIZE),
.SNRQ_SIZE (`LLSNRQ_SIZE),
.CWBQ_SIZE (`LLCWBQ_SIZE),
.DWBQ_SIZE (`LLDWBQ_SIZE),
.DFQQ_SIZE (`LLDFQQ_SIZE),
.LLVQ_SIZE (`LLLLVQ_SIZE),
.FFSQ_SIZE (`LLFFSQ_SIZE),
.PRFQ_SIZE (`LLPRFQ_SIZE),
.PRFQ_STRIDE (`LLPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`LLFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`LLSIMULATED_DRAM_LATENCY_CYCLES)
)
gpu_l2cache
(
.clk (clk),
.reset (reset),
// Core Req (DRAM Fills/WB) To L2 Request
.core_req_valid (l2c_core_req),
.core_req_addr (l2c_core_req_addr),
.core_req_writedata({l2c_core_req_data}),
.core_req_mem_read (l2c_core_req_mem_read),
.core_req_mem_write(l2c_core_req_mem_write),
.core_req_rd (0),
.core_req_wb (l2c_core_req_wb),
.core_req_warp_num (0),
.core_req_pc (0),
// L2 can't accept Core Request
.delay_req (l2c_core_accept),
// Core can't accept L2 Request
.core_no_wb_slot (|l2c_core_no_wb_slot),
// Core Writeback
.core_wb_valid (l2c_wb),
.core_wb_req_rd (),
.core_wb_req_wb (),
.core_wb_warp_num (),
.core_wb_readdata ({l2c_wb_data}),
.core_wb_address (l2c_wb_addr),
.core_wb_pc (),
// L2 Cache DRAM Fill response
.dram_fill_rsp (out_dram_fill_rsp),
.dram_fill_rsp_addr(out_dram_fill_rsp_addr),
.dram_fill_rsp_data({dram_fill_rsp_data_port}),
// L2 Cache can't accept Fill Response
.dram_fill_accept (out_dram_fill_accept),
// L2 Cache DRAM Fill Request
.dram_req (out_dram_req),
.dram_req_write (out_dram_req_write),
.dram_req_read (out_dram_req_read),
.dram_req_addr (out_dram_req_addr),
.dram_req_size (out_dram_req_size),
.dram_req_data ({dram_req_data_port}),
.dram_req_delay (out_dram_req_delay),
// Snoop Response
.dram_req_because_of_wb(dram_req_because_of_wb),
.dram_snp_full (dram_snp_full),
// Snoop Request
.snp_req (llc_snp_req),
.snp_req_addr (llc_snp_req_addr),
.snp_req_delay (llc_snp_req_delay),
.snp_fwd (snp_fwd),
.snp_fwd_addr (snp_fwd_addr),
.snp_fwd_delay (|snp_fwd_delay)
);
endmodule

309
rtl/Vortex_SOC.v
View File

@@ -1,309 +0,0 @@
`include "VX_define.v"
`include "VX_cache_config.v"
module Vortex_SOC (
// Clock
input wire clk,
input wire reset,
// IO
output wire io_valid[`NUMBER_CORES-1:0],
output wire[31:0] io_data [`NUMBER_CORES-1:0],
output wire[31:0] number_cores,
// DRAM Req
output wire out_dram_req,
output wire out_dram_req_write,
output wire out_dram_req_read,
output wire [31:0] out_dram_req_addr,
output wire [31:0] out_dram_req_size,
output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG],
output wire [31:0] out_dram_expected_lat,
input wire out_dram_req_delay,
// DRAM Res
output wire out_dram_fill_accept,
input wire out_dram_fill_rsp,
input wire [31:0] out_dram_fill_rsp_addr,
input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
// LLC Snooping
input wire llc_snp_req,
input wire[31:0] llc_snp_req_addr,
output wire llc_snp_req_delay,
output wire out_ebreak
);
assign number_cores = `NUMBER_CORES;
if (`NUMBER_CLUSTERS == 1) begin
wire[`NUMBER_CORES-1:0] cluster_io_valid;
wire[`NUMBER_CORES-1:0][31:0] cluster_io_data;
genvar curr_c;
for (curr_c = 0; curr_c < `NUMBER_CORES; curr_c=curr_c+1) begin
assign io_valid[curr_c] = cluster_io_valid[curr_c];
assign io_data [curr_c] = cluster_io_data [curr_c];
end
Vortex_Cluster #(.CLUSTER_ID(0)) Vortex_Cluster(
.clk (clk),
.reset (reset),
.io_valid (cluster_io_valid),
.io_data (cluster_io_data),
.out_dram_req (out_dram_req),
.out_dram_req_write (out_dram_req_write),
.out_dram_req_read (out_dram_req_read),
.out_dram_req_addr (out_dram_req_addr),
.out_dram_req_size (out_dram_req_size),
.out_dram_req_data (out_dram_req_data),
.out_dram_expected_lat (out_dram_expected_lat),
.out_dram_req_delay (out_dram_req_delay),
.out_dram_fill_accept (out_dram_fill_accept),
.out_dram_fill_rsp (out_dram_fill_rsp),
.out_dram_fill_rsp_addr(out_dram_fill_rsp_addr),
.out_dram_fill_rsp_data(out_dram_fill_rsp_data),
.llc_snp_req (llc_snp_req),
.llc_snp_req_addr (llc_snp_req_addr),
.llc_snp_req_delay (llc_snp_req_delay),
.out_ebreak (out_ebreak)
);
end else begin
wire snp_fwd;
wire[31:0] snp_fwd_addr;
wire[`NUMBER_CLUSTERS-1:0] snp_fwd_delay;
wire[`NUMBER_CLUSTERS-1:0] per_cluster_out_ebreak;
assign out_ebreak = (&per_cluster_out_ebreak);
// // DRAM Dcache Req
wire[`NUMBER_CLUSTERS-1:0] per_cluster_dram_req;
wire[`NUMBER_CLUSTERS-1:0] per_cluster_dram_req_write;
wire[`NUMBER_CLUSTERS-1:0] per_cluster_dram_req_read;
wire[`NUMBER_CLUSTERS-1:0] [31:0] per_cluster_dram_req_addr;
wire[`NUMBER_CLUSTERS-1:0] [31:0] per_cluster_dram_req_size;
wire[`NUMBER_CLUSTERS-1:0] [31:0] per_cluster_dram_expected_lat;
wire[`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_cluster_dram_req_data;
wire[31:0] per_cluster_dram_req_data_up[`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG];
wire l3c_core_accept;
// // DRAM Dcache Res
wire[`NUMBER_CLUSTERS-1:0] per_cluster_dram_fill_accept;
wire[`NUMBER_CLUSTERS-1:0] per_cluster_dram_fill_rsp;
wire[`NUMBER_CLUSTERS-1:0] [31:0] per_cluster_dram_fill_rsp_addr;
wire[`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_cluster_dram_fill_rsp_data;
wire[31:0] per_cluster_dram_fill_rsp_data_up[`NUMBER_CLUSTERS-1:0][`DBANK_LINE_SIZE_RNG];
wire[`NUMBER_CLUSTERS-1:0][`NUMBER_CORES_PER_CLUSTER-1:0] per_cluster_io_valid;
wire[`NUMBER_CLUSTERS-1:0][`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_cluster_io_data;
genvar curr_c;
genvar curr_cc;
genvar curr_word;
for (curr_c = 0; curr_c < `NUMBER_CLUSTERS; curr_c =curr_c+1) begin
for (curr_cc = 0; curr_cc < `NUMBER_CORES_PER_CLUSTER; curr_cc=curr_cc+1) begin
assign io_valid[curr_cc+(curr_c*`NUMBER_CORES_PER_CLUSTER)] = per_cluster_io_valid[curr_c][curr_cc];
assign io_data [curr_cc+(curr_c*`NUMBER_CORES_PER_CLUSTER)] = per_cluster_io_data [curr_c][curr_cc];
end
for (curr_word = 0; curr_word < `DBANK_LINE_SIZE_WORDS; curr_word = curr_word+1) begin
assign per_cluster_dram_req_data [curr_c][curr_word] = per_cluster_dram_req_data_up [curr_c][curr_word];
assign per_cluster_dram_fill_rsp_data_up[curr_c][curr_word] = per_cluster_dram_fill_rsp_data[curr_c][curr_word];
end
end
genvar curr_cluster;
for (curr_cluster = 0; curr_cluster < `NUMBER_CLUSTERS; curr_cluster=curr_cluster+1) begin
Vortex_Cluster #(.CLUSTER_ID(curr_cluster)) Vortex_Cluster(
.clk (clk),
.reset (reset),
.io_valid (per_cluster_io_valid [curr_cluster]),
.io_data (per_cluster_io_data [curr_cluster]),
.out_dram_req (per_cluster_dram_req [curr_cluster]),
.out_dram_req_write (per_cluster_dram_req_write [curr_cluster]),
.out_dram_req_read (per_cluster_dram_req_read [curr_cluster]),
.out_dram_req_addr (per_cluster_dram_req_addr [curr_cluster]),
.out_dram_req_size (per_cluster_dram_req_size [curr_cluster]),
.out_dram_req_data (per_cluster_dram_req_data_up [curr_cluster]),
.out_dram_expected_lat (per_cluster_dram_expected_lat [curr_cluster]),
.out_dram_req_delay (l3c_core_accept),
.out_dram_fill_accept (per_cluster_dram_fill_accept [curr_cluster]),
.out_dram_fill_rsp (per_cluster_dram_fill_rsp [curr_cluster]),
.out_dram_fill_rsp_addr(per_cluster_dram_fill_rsp_addr [curr_cluster]),
.out_dram_fill_rsp_data(per_cluster_dram_fill_rsp_data_up[curr_cluster]),
.llc_snp_req (snp_fwd),
.llc_snp_req_addr (snp_fwd_addr),
.llc_snp_req_delay (snp_fwd_delay[curr_cluster]),
.out_ebreak (per_cluster_out_ebreak [curr_cluster])
);
end
//////////////////// L3 Cache ////////////////////
wire[`L3NUMBER_REQUESTS-1:0] l3c_core_req;
wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_write;
wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_read;
wire[`L3NUMBER_REQUESTS-1:0][31:0] l3c_core_req_addr;
wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_core_req_data;
wire[`L3NUMBER_REQUESTS-1:0][1:0] l3c_core_req_wb;
wire[`L3NUMBER_REQUESTS-1:0] l3c_core_no_wb_slot;
wire[`L3NUMBER_REQUESTS-1:0] l3c_wb;
wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr;
wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_wb_data;
wire[`DBANK_LINE_SIZE_RNG][31:0] dram_req_data_port;
wire[`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data_port;
genvar llb_index;
for (llb_index = 0; llb_index < `DBANK_LINE_SIZE_WORDS; llb_index=llb_index+1) begin
assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index];
assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index];
end
//
genvar l3c_curr_cluster;
for (l3c_curr_cluster = 0; l3c_curr_cluster < `L3NUMBER_REQUESTS; l3c_curr_cluster=l3c_curr_cluster+1) begin
// Core Request
assign l3c_core_req [l3c_curr_cluster] = per_cluster_dram_req [l3c_curr_cluster];
assign l3c_core_req_mem_write [l3c_curr_cluster] = per_cluster_dram_req_write[l3c_curr_cluster] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
assign l3c_core_req_mem_read [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? `LW_MEM_READ : `NO_MEM_READ;
assign l3c_core_req_wb [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? 1 : 0;
assign l3c_core_req_addr [l3c_curr_cluster] = per_cluster_dram_req_addr [l3c_curr_cluster];
assign l3c_core_req_data [l3c_curr_cluster] = per_cluster_dram_req_data [l3c_curr_cluster];
// Core can't accept Response
assign l3c_core_no_wb_slot [l3c_curr_cluster] = ~per_cluster_dram_fill_accept[l3c_curr_cluster];
// Cache Fill Response
assign per_cluster_dram_fill_rsp [l3c_curr_cluster] = l3c_wb [l3c_curr_cluster];
assign per_cluster_dram_fill_rsp_data[l3c_curr_cluster] = l3c_wb_data[l3c_curr_cluster];
assign per_cluster_dram_fill_rsp_addr[l3c_curr_cluster] = l3c_wb_addr[l3c_curr_cluster];
end
wire dram_snp_full;
wire dram_req_because_of_wb;
VX_cache #(
.CACHE_SIZE_BYTES (`L3CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (`L3NUMBER_BANKS),
.WORD_SIZE_BYTES (`L3WORD_SIZE_BYTES),
.NUMBER_REQUESTS (`L3NUMBER_REQUESTS),
.STAGE_1_CYCLES (`L3STAGE_1_CYCLES),
.FUNC_ID (`LLFUNC_ID),
.REQQ_SIZE (`L3REQQ_SIZE),
.MRVQ_SIZE (`L3MRVQ_SIZE),
.DFPQ_SIZE (`L3DFPQ_SIZE),
.SNRQ_SIZE (`L3SNRQ_SIZE),
.CWBQ_SIZE (`L3CWBQ_SIZE),
.DWBQ_SIZE (`L3DWBQ_SIZE),
.DFQQ_SIZE (`L3DFQQ_SIZE),
.LLVQ_SIZE (`L3LLVQ_SIZE),
.FFSQ_SIZE (`L3FFSQ_SIZE),
.PRFQ_SIZE (`L3PRFQ_SIZE),
.PRFQ_STRIDE (`L3PRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`L3SIMULATED_DRAM_LATENCY_CYCLES)
)
gpu_l3cache
(
.clk (clk),
.reset (reset),
// Core Req (DRAM Fills/WB) To L2 Request
.core_req_valid (l3c_core_req),
.core_req_addr (l3c_core_req_addr),
.core_req_writedata({l3c_core_req_data}),
.core_req_mem_read (l3c_core_req_mem_read),
.core_req_mem_write(l3c_core_req_mem_write),
.core_req_rd (0),
.core_req_wb (l3c_core_req_wb),
.core_req_warp_num (0),
.core_req_pc (0),
// L2 can't accept Core Request
.delay_req (l3c_core_accept),
// Core can't accept L2 Request
.core_no_wb_slot (|l3c_core_no_wb_slot),
// Core Writeback
.core_wb_valid (l3c_wb),
.core_wb_req_rd (),
.core_wb_req_wb (),
.core_wb_warp_num (),
.core_wb_readdata ({l3c_wb_data}),
.core_wb_address (l3c_wb_addr),
.core_wb_pc (),
// L2 Cache DRAM Fill response
.dram_fill_rsp (out_dram_fill_rsp),
.dram_fill_rsp_addr(out_dram_fill_rsp_addr),
.dram_fill_rsp_data({dram_fill_rsp_data_port}),
// L2 Cache can't accept Fill Response
.dram_fill_accept (out_dram_fill_accept),
// L2 Cache DRAM Fill Request
.dram_req (out_dram_req),
.dram_req_write (out_dram_req_write),
.dram_req_read (out_dram_req_read),
.dram_req_addr (out_dram_req_addr),
.dram_req_size (out_dram_req_size),
.dram_req_data ({dram_req_data_port}),
.dram_req_delay (out_dram_req_delay),
// Snoop Response
.dram_req_because_of_wb(dram_req_because_of_wb),
.dram_snp_full (dram_snp_full),
// Snoop Request
.snp_req (llc_snp_req),
.snp_req_addr (llc_snp_req_addr),
.snp_req_delay (llc_snp_req_delay),
// Snoop Forward
.snp_fwd (snp_fwd),
.snp_fwd_addr (snp_fwd_addr),
.snp_fwd_delay (|snp_fwd_delay)
);
end
endmodule

56
rtl/byte_enabled_simple_dual_port_ram.v
View File

@@ -1,56 +0,0 @@
`include "VX_define.v"
module byte_enabled_simple_dual_port_ram
(
input we, clk,
input wire reset,
input wire[4:0] waddr, raddr1, raddr2,
input wire[`NT_M1:0] be,
input wire[`NT_M1:0][31:0] wdata,
output reg[`NT_M1:0][31:0] q1, q2
);
// integer regi;
// integer threadi;
// Thread Byte Bit
logic [`NT_M1:0][3:0][7:0] GPR[31:0];
// initial begin
// for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] = 0;
// end
integer ini;
always @(posedge clk, posedge reset) begin
// TODO Clearing ram not currently supported on FPGA.
if (reset) begin
// `ifdef ASIC
for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] <= 0;
// `endif
end
else if(we) begin
integer thread_ind;
for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin
if(be[thread_ind]) GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
if(be[thread_ind]) GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
if(be[thread_ind]) GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
if(be[thread_ind]) GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
end
end
// $display("^^^^^^^^^^^^^^^^^^^^^^^");
// for (regi = 0; regi <= 31; regi = regi + 1) begin
// for (threadi = 0; threadi <= `NT_M1; threadi = threadi + 1) begin
// if (GPR[regi][threadi] != 0) $display("$%d: %h",regi, GPR[regi][threadi]);
// end
// end
end
assign q1 = GPR[raddr1];
assign q2 = GPR[raddr2];
// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];
endmodule

12
rtl/cache/Makefile vendored
View File

@@ -1,12 +0,0 @@
all: RUNFILE
VERILATOR:
verilator --compiler gcc --Wno-UNOPTFLAT -Wall --trace -cc VX_d_cache_encapsulate.v -Iinterfaces/ --exe d_cache_test_bench.cpp -CFLAGS -std=c++11
RUNFILE: VERILATOR
(cd obj_dir && make -j -f VVX_d_cache_encapsulate.mk)
clean:
rm ./obj_dir/*

46
rtl/cache/Notes vendored
View File

@@ -1,46 +0,0 @@
Notes
8 kB L1 Data Cache | 16 kB L1 I cache (maybe)
[tag index offset_remaining_block bank wordOffset], use a blocksize of 128 bytes between memory and cache. So each bank gets 16 bytes.
total offset is b its
4 bits new offset, 2 bits block, 2 bits word offset
xxxxxxxIIIIIIIIoobbbyy
9876543210
bbbyyyyy
o = index into block offset
b = bank
y = word offset
I = index into cach
6 bits indexes (64 indeces) No ways || 16 indexes with 4 ways
Rest of the bits are tag bits
blocks / banks = 16 bytes, 8 banks. 128 bytes. 256 indexes (height). width is 16 bytes. 4 words per block (per bank). 17 bit tag
gtkwave ___.vcd
// Splitting it up
// word byte
wire[127:0][3:0] data_from_ram;
// word byte bank
wire[15:0][3:0] bank_data_n[3:0]
integer i;
for (i = 0; i < something; i+=8)
{
bank_data_n[0][i/8] = data_from_ram[i+0]
bank_data_n[1][i/8] = data_from_ram[i+1]
bank_data_n[2][i/8] = data_from_ram[i+2]
bank_data_n[3][i/8] = data_from_ram[i+3]
bank_data_n[4][i/8] = data_from_ram[i+4]
bank_data_n[5][i/8] = data_from_ram[i+5]
bank_data_n[6][i/8] = data_from_ram[i+6]
bank_data_n[7][i/8] = data_from_ram[i+7]
}
With Cache. If miss. Go to memory, grab all data, replace that data in the cache. Generate a new request, feed that into the cache (this one will hit), return that

253
rtl/cache/VX_Cache_Bank.v vendored
View File

@@ -1,253 +0,0 @@
// To Do: Change way_id_out to an internal register which holds when in between access and finished.
// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
// Also make sure all possible output states are transmitted back to the bank correctly
`include "VX_define.v"
module VX_Cache_Bank
#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter LOG_NUM_BANKS = 3,
parameter NUM_REQ = 8,
parameter LOG_NUM_REQ = 3,
parameter NUM_IND = 8,
parameter CACHE_WAY_INDEX = 1,
parameter NUM_WORDS_PER_BLOCK = 4,
parameter OFFSET_SIZE_START = 0,
parameter OFFSET_SIZE_END = 1,
parameter TAG_SIZE_START = 0,
parameter TAG_SIZE_END = 16,
parameter IND_SIZE_START = 0,
parameter IND_SIZE_END = 7,
parameter ADDR_TAG_START = 15,
parameter ADDR_TAG_END = 31,
parameter ADDR_OFFSET_START = 5,
parameter ADDR_OFFSET_END = 6,
parameter ADDR_IND_START = 7,
parameter ADDR_IND_END = 14
)
(
clk,
rst,
state,
read_or_write, // Read = 0 | Write = 1
i_p_mem_read,
i_p_mem_write,
valid_in,
//write_from_mem,
actual_index,
o_tag,
block_offset,
writedata,
fetched_writedata,
byte_select,
readdata,
hit,
//miss,
eviction_wb, // Need to evict
eviction_addr, // What's the eviction tag
data_evicted,
evicted_way
);
// localparam NUMBER_BANKS = `CACHE_BANKS;
// localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4);
// localparam NUMBER_INDEXES = `NUM_IND;
localparam CACHE_IDLE = 0; // Idle
localparam SEND_MEM_REQ = 1; // Write back this block into memory
localparam RECIV_MEM_RSP = 2;
localparam BLOCK_NUM_BITS = `CLOG2(CACHE_BLOCK);
// Inputs
input wire rst;
input wire clk;
input wire [3:0] state;
//input wire write_from_mem;
// Reading Data
input wire[IND_SIZE_END:IND_SIZE_START] actual_index;
input wire[TAG_SIZE_END:TAG_SIZE_START] o_tag; // When write_from_mem = 1, o_tag is the new tag
input wire[OFFSET_SIZE_END:OFFSET_SIZE_START] block_offset;
input wire[31:0] writedata;
input wire valid_in;
input wire read_or_write; // Specifies if it is a read or write operation
input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
input wire[2:0] i_p_mem_read;
input wire[2:0] i_p_mem_write;
input wire[1:0] byte_select;
input wire[CACHE_WAY_INDEX-1:0] evicted_way;
// Outputs
// Normal shit
output wire[31:0] readdata;
output wire hit;
//output wire miss;
// Eviction Data (Notice)
output wire eviction_wb; // Need to evict
output wire[31:0] eviction_addr; // What's the eviction tag
// Eviction Data (Extraction)
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use;
wire[TAG_SIZE_END:TAG_SIZE_START] tag_use;
wire[TAG_SIZE_END:TAG_SIZE_START] eviction_tag;
wire valid_use;
wire dirty_use;
wire access;
wire write_from_mem;
wire miss; // -10/21
wire[CACHE_WAY_INDEX-1:0] way_to_update;
assign miss = (tag_use != o_tag) && valid_use && valid_in;
assign data_evicted = data_use;
// assign eviction_wb = miss && (dirty_use != 1'b0) && valid_use;
assign eviction_wb = (dirty_use != 1'b0);
assign eviction_tag = tag_use;
assign access = (state == CACHE_IDLE) && valid_in;
assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in; // TODO
assign hit = (access && (tag_use == o_tag) && valid_use);
//assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data
assign eviction_addr = {eviction_tag, actual_index, {(BLOCK_NUM_BITS){1'b0}}}; // Fix with actual data
wire lw = (i_p_mem_read == `LW_MEM_READ);
wire lb = (i_p_mem_read == `LB_MEM_READ);
wire lh = (i_p_mem_read == `LH_MEM_READ);
wire lhu = (i_p_mem_read == `LHU_MEM_READ);
wire lbu = (i_p_mem_read == `LBU_MEM_READ);
wire sw = (i_p_mem_write == `SW_MEM_WRITE);
wire sb = (i_p_mem_write == `SB_MEM_WRITE);
wire sh = (i_p_mem_write == `SH_MEM_WRITE);
wire b0 = (byte_select == 0);
wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
wire[31:0] data_unQual = (b0 || lw) ? (data_use[block_offset] ) :
b1 ? (data_use[block_offset] >> 8) :
b2 ? (data_use[block_offset] >> 16) :
(data_use[block_offset] >> 24);
wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF);
wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF);
wire[31:0] lbu_data = (data_unQual & 32'hFF);
wire[31:0] lhu_data = (data_unQual & 32'hFFFF);
wire[31:0] lw_data = (data_unQual);
wire[31:0] sw_data = writedata;
wire[31:0] sb_data = b1 ? {{16{1'b0}}, writedata[7:0], { 8{1'b0}}} :
b2 ? {{ 8{1'b0}}, writedata[7:0], {16{1'b0}}} :
b3 ? {{ 0{1'b0}}, writedata[7:0], {24{1'b0}}} :
writedata;
wire[31:0] sh_data = b2 ? {writedata[15:0], {16{1'b0}}} : writedata;
wire[31:0] use_write_data = sb ? sb_data :
sh ? sh_data :
sw_data;
wire[31:0] data_Qual = lb ? lb_data :
lh ? lh_data :
lhu ? lhu_data :
lbu ? lbu_data :
lw_data;
assign readdata = (access) ? data_Qual : 32'b0; // Fix with actual data
wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
genvar g;
generate
for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin : write_enables
wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
assign we[g] = (write_from_mem) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :
4'b0000;
// assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0;
assign data_write[g] = write_from_mem ? fetched_writedata[g] : use_write_data;
assign way_to_update = evicted_way;
end
endgenerate
VX_cache_data_per_index #(
.CACHE_WAYS (CACHE_WAYS),
.NUM_IND (NUM_IND),
.CACHE_WAY_INDEX (CACHE_WAY_INDEX),
.NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK),
.TAG_SIZE_START (TAG_SIZE_START),
.TAG_SIZE_END (TAG_SIZE_END),
.IND_SIZE_START (IND_SIZE_START),
.IND_SIZE_END (IND_SIZE_END)) data_structures(
.clk (clk),
.rst (rst),
.valid_in (valid_in),
.state (state),
// Inputs
.addr (actual_index),
.we (we),
.evict (write_from_mem),
.data_write (data_write),
.tag_write (o_tag),
.way_to_update(way_to_update),
// Outputs
.tag_use (tag_use),
.data_use (data_use),
.valid_use (valid_use),
.dirty_use (dirty_use)
);
endmodule

30
rtl/cache/VX_cache_bank_valid.v vendored
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@@ -1,30 +0,0 @@
`include "VX_define.v"
module VX_cache_bank_valid
#(
parameter NUMBER_BANKS = 8,
parameter LOG_NUM_BANKS = 3,
parameter NUM_REQ = 1
)
(
input wire [NUM_REQ-1:0] i_p_valid,
input wire [NUM_REQ-1:0][31:0] i_p_addr,
output reg [NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks
);
generate
integer t_id;
always @(*) begin
thread_track_banks = 0;
for (t_id = 0; t_id < NUM_REQ; t_id = t_id + 1)
begin
if (NUMBER_BANKS != 1) begin
thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id];
end else begin
thread_track_banks[0][t_id] = i_p_valid[t_id];
end
end
end
endgenerate
endmodule

231
rtl/cache/VX_cache_data.v vendored
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@@ -1,231 +0,0 @@
`include "VX_define.v"
module VX_cache_data
#(
parameter NUM_IND = 8,
parameter NUM_WORDS_PER_BLOCK = 4,
parameter TAG_SIZE_START = 0,
parameter TAG_SIZE_END = 16,
parameter IND_SIZE_START = 0,
parameter IND_SIZE_END = 7
)
(
input wire clk, rst, // Clock
// `ifdef PARAM
// Addr
input wire[IND_SIZE_END:IND_SIZE_START] addr,
// WE
input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict,
// Data
input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write,
input wire[TAG_SIZE_END:TAG_SIZE_START] tag_write,
output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use,
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use,
output wire dirty_use
// `else
// // Addr
// input wire[7:0] addr,
// // WE
// input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
// input wire evict,
// // Data
// input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
// input wire[16:0] tag_write,
// output wire[16:0] tag_use,
// output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
// output wire valid_use,
// output wire dirty_use
// `endif
);
//localparam NUMBER_BANKS = CACHE_BANKS;
//localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//localparam NUMBER_INDEXES = NUM_IND;
wire currently_writing = (|we);
wire update_dirty = ((!dirty_use) && currently_writing) || (evict);
wire dirt_new = evict ? 0 : (|we);
`ifndef SYN
// (3:0) 4 bytes
reg[NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUM_IND-1:0]; // Actual Data
reg[TAG_SIZE_END:TAG_SIZE_START] tag[NUM_IND-1:0];
reg valid[NUM_IND-1:0];
reg dirty[NUM_IND-1:0];
// 16 bytes
assign data_use = data[addr]; // Read Port
assign tag_use = tag[addr];
assign valid_use = valid[addr];
assign dirty_use = dirty[addr];
integer f;
integer ini_ind;
always @(posedge clk, posedge rst) begin : update_all
if (rst) begin
for (ini_ind = 0; ini_ind < NUM_IND; ini_ind=ini_ind+1) begin
//data[ini_ind] <= 0;
//tag[ini_ind] <= 0;
valid[ini_ind] <= 0;
//dirty[ini_ind] <= 0;
end
end else begin
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
if (evict) tag[addr] <= tag_write;
if (evict) valid[addr] <= 1;
for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
if (we[f][3]) data[addr][f][3] <= data_write[f][31:24];
end
end
end
`else
wire[IND_SIZE_END:IND_SIZE_START] use_addr = addr;
wire cena = 1;
wire cenb_d = (|we);
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
genvar cur_b;
for (cur_b = 0; cur_b < NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}};
end
assign data_use = data_out_d;
// Using ASIC MEM
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 data (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(data_out_d),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(use_addr),
.CLKB(clk),
.CENB(cenb_d),
.WENB(write_bit_mask_d),
.AB(use_addr),
.DB(wdata_d),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(5'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
wire[16:0] old_tag;
wire old_valid;
wire old_dirty;
wire[16:0] new_tag = evict ? tag_write : old_tag;
wire new_valid = evict ? 1 : old_valid;
wire new_dirty = update_dirty ? dirt_new : old_dirty;
wire cenb_m = (evict || update_dirty);
wire[19-1:0][31:0] write_bit_mask_m = cenb_m ? 19'b0 : 19'b1;
// Try to fix the error in memory conneciton, modified by Lingjun Zhu on Oct. 28 2019
// wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid};
// wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m;
wire[19-1:0] wdata_m = {new_tag, new_dirty, new_valid};
wire[19-1:0] data_out_m;
assign {old_tag, old_dirty, old_valid} = data_out_m;
assign dirty_use = old_dirty;
assign valid_use = old_valid;
assign tag_use = old_tag;
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x19_wm0 meta (
.CENYA(),
.AYA(),
.CENYB(),
// .WENYB(),
.AYB(),
.QA(data_out_m),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(use_addr),
.CLKB(clk),
.CENB(cenb_m),
// .WENB(write_bit_mask_m),
.AB(use_addr),
.DB(wdata_m),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
// .TWENB(128'b0),
.TAB(5'b0),
.TDB(19'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
`endif
endmodule

165
rtl/cache/VX_cache_data_per_index.v vendored
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@@ -1,165 +0,0 @@
`include "VX_define.v"
module VX_cache_data_per_index
#(
parameter CACHE_WAYS = 1,
parameter NUM_IND = 8,
parameter CACHE_WAY_INDEX = 1,
parameter NUM_WORDS_PER_BLOCK = 4,
parameter TAG_SIZE_START = 0,
parameter TAG_SIZE_END = 16,
parameter IND_SIZE_START = 0,
parameter IND_SIZE_END = 7
)
(
input wire clk, // Clock
input wire rst,
input wire valid_in,
input wire [3:0] state,
// Addr
input wire[IND_SIZE_END:IND_SIZE_START] addr,
// WE
input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict,
input wire[CACHE_WAY_INDEX-1:0] way_to_update,
// Data
input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
input wire[TAG_SIZE_END:TAG_SIZE_START] tag_write,
output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use,
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use,
output wire dirty_use
);
//localparam NUMBER_BANKS = CACHE_BANKS;
//localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//localparam NUMBER_INDEXES = `DCACHE_NUM_IND;
wire [CACHE_WAYS-1:0][TAG_SIZE_END:TAG_SIZE_START] tag_use_per_way;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way;
wire [CACHE_WAYS-1:0] valid_use_per_way;
wire [CACHE_WAYS-1:0] dirty_use_per_way;
wire [CACHE_WAYS-1:0] hit_per_way;
// reg [CACHE_WAY_INDEX-1:0] eviction_way_index;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
wire [CACHE_WAYS-1:0] write_from_mem_per_way;
wire invalid_found;
wire [CACHE_WAY_INDEX-1:0] way_index;
wire [CACHE_WAY_INDEX-1:0] invalid_index;
localparam CACHE_IDLE = 0; // Idle
localparam SEND_MEM_REQ = 1; // Write back this block into memory
localparam RECIV_MEM_RSP = 2;
generate
if(CACHE_WAYS != 1) begin
VX_generic_priority_encoder #(.N(CACHE_WAYS)) valid_index
(
.valids(~valid_use_per_way),
.index (invalid_index),
.found (invalid_found)
);
VX_generic_priority_encoder #(.N(CACHE_WAYS)) way_indexing
(
.valids(hit_per_way),
.index (way_index),
.found ()
);
end
else begin
assign way_index = 0;
assign invalid_found = (valid_use_per_way == 1'b0) ? 1 : 0;
assign invalid_index = 0;
end
endgenerate
// wire hit = |hit_per_way;
// wire miss = ~hit;
// wire update = |we && !miss;
// wire valid = &valid_use_per_way;
wire[CACHE_WAY_INDEX-1:0] way_use_Qual;
assign way_use_Qual = (state != CACHE_IDLE) ? way_to_update : way_index;
assign tag_use = tag_use_per_way[way_use_Qual];
assign data_use = data_use_per_way[way_use_Qual];
assign valid_use = valid_use_per_way[way_use_Qual];
assign dirty_use = dirty_use_per_way[way_use_Qual];
// assign tag_use = hit ? tag_use_per_way[way_index] : (valid ? tag_use_per_way[eviction_way_index] : (invalid_found ? tag_use_per_way[invalid_index] : 0));
// assign data_use = hit ? data_use_per_way[way_index] : (valid ? data_use_per_way[eviction_way_index] : (invalid_found ? data_use_per_way[invalid_index] : 0));
// assign valid_use = hit ? valid_use_per_way[way_index] : (valid ? valid_use_per_way[eviction_way_index] : (invalid_found ? valid_use_per_way[invalid_index] : 0));
// assign dirty_use = hit ? dirty_use_per_way[way_index] : (valid ? dirty_use_per_way[eviction_way_index] : (invalid_found ? dirty_use_per_way[invalid_index] : 0));
genvar ways;
generate
for(ways=0; ways < CACHE_WAYS; ways = ways + 1) begin : each_way
assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
assign write_from_mem_per_way[ways] = evict && (ways == way_use_Qual);
assign we_per_way[ways] = (ways == way_use_Qual) ? (we) : 0;
assign data_write_per_way[ways] = data_write;
// assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
// assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_use_Qual) ? (we) : 0) : 0;
// assign data_write_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_use_Qual) ? data_write : 0) : 0;
// assign write_from_mem_per_way[ways] = (evict == 1'b1) ? ((ways == way_use_Qual) ? 1 : 0) : 0;
VX_cache_data #(
.NUM_IND (NUM_IND),
.NUM_WORDS_PER_BLOCK (NUM_WORDS_PER_BLOCK),
.TAG_SIZE_START (TAG_SIZE_START),
.TAG_SIZE_END (TAG_SIZE_END),
.IND_SIZE_START (IND_SIZE_START),
.IND_SIZE_END (IND_SIZE_END)) data_structures(
.clk (clk),
.rst (rst),
// Inputs
.addr (addr),
.we (we_per_way[ways]),
.evict (write_from_mem_per_way[ways]),
.data_write(data_write_per_way[ways]),
.tag_write (tag_write),
// Outputs
.tag_use (tag_use_per_way[ways]),
.data_use (data_use_per_way[ways]),
.valid_use (valid_use_per_way[ways]),
.dirty_use (dirty_use_per_way[ways])
);
end
endgenerate
// always @(posedge clk or posedge rst) begin
// if (rst) begin
// eviction_way_index <= 0;
// end else begin
// // if((miss && dirty_use && valid_use && !evict && valid_in)) begin // can be either evict or invalid cache entries
// if((state == SEND_MEM_REQ)) begin // can be either evict or invalid cache entries
// if((eviction_way_index+1) == CACHE_WAYS) begin
// eviction_way_index <= 0;
// end else begin
// eviction_way_index <= (eviction_way_index + 1);
// end
// end
// end
// end
endmodule

389
rtl/cache/VX_d_cache.v vendored
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@@ -1,389 +0,0 @@
// Cache Memory (8way 4word) //
// i_ means input port //
// o_ means output port //
// _p_ means data exchange with processor //
// _m_ means data exchange with memory //
// TO DO:
// - Send in a response from memory of what the data is from the test bench
`include "VX_define.v"
//`include "VX_Cache_Bank.v"
//`include "VX_cache_bank_valid.v"
//`include "VX_priority_encoder.v"
//`include "VX_priority_encoder_w_mask.v"
module VX_d_cache
#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter LOG_NUM_BANKS = 3,
parameter NUM_REQ = 8,
parameter LOG_NUM_REQ = 3,
parameter NUM_IND = 8,
parameter CACHE_WAY_INDEX = 1,
parameter NUM_WORDS_PER_BLOCK = 4,
parameter OFFSET_SIZE_START = 0,
parameter OFFSET_SIZE_END = 1,
parameter TAG_SIZE_START = 0,
parameter TAG_SIZE_END = 16,
parameter IND_SIZE_START = 0,
parameter IND_SIZE_END = 7,
parameter ADDR_TAG_START = 15,
parameter ADDR_TAG_END = 31,
parameter ADDR_OFFSET_START = 5,
parameter ADDR_OFFSET_END = 6,
parameter ADDR_IND_START = 7,
parameter ADDR_IND_END = 14,
parameter MEM_ADDR_REQ_MASK = 32'hffffffc0
)
(
clk,
rst,
i_p_addr,
//i_p_byte_en,
i_p_writedata,
i_p_read_or_write, // 0 = Read | 1 = Write
i_p_mem_read,
i_p_mem_write,
i_p_valid,
//i_p_write,
o_p_readdata,
o_p_delay, // 0 = all threads done | 1 = Still threads that need to
o_m_evict_addr,
o_m_read_addr,
o_m_writedata,
o_m_read_or_write, // 0 = Read | 1 = Write
o_m_valid,
i_m_readdata,
i_m_ready
);
//parameter NUMBER_BANKS = `CACHE_BANKS;
//localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4);
//localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS);
localparam CACHE_IDLE = 0; // Idle
localparam SEND_MEM_REQ = 1; // Write back this block into memory
localparam RECIV_MEM_RSP = 2;
//parameter cache_entry = 9;
input wire clk, rst;
input wire [NUM_REQ-1:0] i_p_valid;
input wire [NUM_REQ-1:0][31:0] i_p_addr; // FIXME
input wire [NUM_REQ-1:0][31:0] i_p_writedata;
input wire i_p_read_or_write; //, i_p_write;
output reg [NUM_REQ-1:0][31:0] o_p_readdata;
output wire o_p_delay;
output reg [31:0] o_m_evict_addr; // Address is xxxxxxxxxxoooobbbyy
output reg [31:0] o_m_read_addr;
output reg o_m_valid;
output reg[CACHE_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
output reg o_m_read_or_write; //, o_m_write;
input wire[CACHE_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire i_m_ready;
input wire[2:0] i_p_mem_read;
input wire[2:0] i_p_mem_write;
// Buffer for final data
reg [NUM_REQ-1:0][31:0] final_data_read;
reg [NUM_REQ-1:0][31:0] new_final_data_read;
wire[NUM_REQ-1:0][31:0] new_final_data_read_Qual;
assign o_p_readdata = new_final_data_read_Qual;
reg[CACHE_WAY_INDEX-1:0] global_way_to_evict;
wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
wire[CACHE_BANKS - 1 : 0][LOG_NUM_REQ-1:0] index_per_bank; // Index of thread each bank will try to service
wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank
wire[CACHE_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank
wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank
wire[CACHE_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank
wire[CACHE_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss
wire[CACHE_BANKS-1:0] eviction_wb;
reg[CACHE_BANKS-1:0] eviction_wb_old;
// wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_new;
// reg [CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_old;
// wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] way_used;
// Internal State
reg [3:0] state;
wire[3:0] new_state;
wire[NUM_REQ-1:0] use_valid; // Valid used throught the code
reg[NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss)
wire[NUM_REQ-1:0] new_stored_valid; // New stored valid
reg[CACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
reg[31:0] miss_addr;
// reg[31:0] evict_addr;
wire curr_processor_request_valid = (|i_p_valid);
assign use_valid = (stored_valid == 0) ? i_p_valid : stored_valid;
VX_cache_bank_valid #(.NUMBER_BANKS (CACHE_BANKS),
.LOG_NUM_BANKS (LOG_NUM_BANKS),
.NUM_REQ (NUM_REQ)) multip_banks(
.i_p_valid (use_valid),
.i_p_addr (i_p_addr),
.thread_track_banks(thread_track_banks)
);
reg[NUM_REQ-1:0] threads_serviced_Qual;
reg[NUM_REQ-1:0] debug_hit_per_bank_mask[CACHE_BANKS-1:0];
genvar bid;
generate
for (bid = 0; bid < CACHE_BANKS; bid=bid+1) begin : chooose_threads
wire[NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid];
wire[LOG_NUM_REQ-1:0] use_thread_index = index_per_bank[bid];
wire use_write_final_data = hit_per_bank[bid];
wire[31:0] use_data_final_data = readdata_per_bank[bid];
VX_priority_encoder_w_mask #(.N(NUM_REQ)) choose_thread(
.valids(use_threads_track_banks),
.mask (use_mask_per_bank[bid]),
.index (index_per_bank[bid]),
.found (valid_per_bank[bid])
);
assign debug_hit_per_bank_mask[bid] = {NUM_REQ{hit_per_bank[bid]}};
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
end
endgenerate
integer test_bid;
always @(*) begin
new_final_data_read = 0;
for (test_bid=0; test_bid < CACHE_BANKS; test_bid=test_bid+1)
begin
if (hit_per_bank[test_bid]) begin
new_final_data_read[index_per_bank[test_bid]] = readdata_per_bank[test_bid];
end
end
end
wire[CACHE_BANKS - 1 : 0] detect_bank_miss;
//assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] |
// threads_serviced_per_bank[2] | threads_serviced_per_bank[3] |
// threads_serviced_per_bank[4] | threads_serviced_per_bank[5] |
// threads_serviced_per_bank[6] | threads_serviced_per_bank[7];
integer bbid;
always @(*) begin
threads_serviced_Qual = 0;
for (bbid = 0; bbid < CACHE_BANKS; bbid=bbid+1)
begin
threads_serviced_Qual = threads_serviced_Qual | threads_serviced_per_bank[bbid];
end
end
genvar tid;
generate
for (tid = 0; tid < NUM_REQ; tid =tid+1) begin : new_final_data_read_Qual_setup
assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid];
end
endgenerate
assign detect_bank_miss = (valid_per_bank & ~hit_per_bank);
wire delay;
assign delay = (new_stored_valid != 0) || (state != CACHE_IDLE); // add other states
assign o_p_delay = delay;
wire[CACHE_BANKS - 1 : 0][LOG_NUM_REQ-1:0] send_index_to_bank = index_per_bank;
wire[LOG_NUM_BANKS-1:0] miss_bank_index;
wire miss_found;
VX_generic_priority_encoder #(.N(CACHE_BANKS)) get_miss_index
(
.valids(detect_bank_miss),
.index (miss_bank_index),
.found (miss_found)
);
assign new_state = ((state == CACHE_IDLE) && (|detect_bank_miss)) ? SEND_MEM_REQ :
(state == SEND_MEM_REQ) ? RECIV_MEM_RSP :
((state == RECIV_MEM_RSP) && !i_m_ready) ? RECIV_MEM_RSP :
CACHE_IDLE;
// Handle if there is more than one miss
assign new_stored_valid = use_valid & (~threads_serviced_Qual);
wire update_global_way_to_evict = ((state == RECIV_MEM_RSP) && (new_state == CACHE_IDLE)) && (CACHE_WAYS > 1);
///////////////////////////////////////////////////////////////////////
genvar cur_t;
integer init_b;
always @(posedge clk, posedge rst) begin
if (rst) begin
final_data_read <= 0;
// new_final_data_read = 0;
state <= 0;
stored_valid <= 0;
// eviction_addr_per_bank <= 0;
miss_addr <= 0;
// evict_addr <= 0;
// threads_serviced_Qual = 0;
// for (init_b = 0; init_b < NUMBER_BANKS; init_b=init_b+1)
// begin
// debug_hit_per_bank_mask[init_b] <= 0;
// end
// evicted_way_old <= 0;
// eviction_wb_old <= 0;
global_way_to_evict <= 0;
end else begin
global_way_to_evict <= (update_global_way_to_evict) ? (global_way_to_evict+1) : global_way_to_evict;
state <= new_state;
stored_valid <= new_stored_valid;
if (state == CACHE_IDLE) begin
if (miss_found) begin
miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
// evict_addr <= eviction_addr_per_bank[miss_bank_index];
end else begin
miss_addr <= 0;
// evict_addr <= 0;
end
end
final_data_read <= new_final_data_read_Qual;
// evicted_way_old <= evicted_way_new;
// eviction_wb_old <= eviction_wb;
end
end
genvar bank_id;
generate
for (bank_id = 0; bank_id < CACHE_BANKS; bank_id = bank_id + 1) begin : cache_banks
wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? miss_addr :
(state == RECIV_MEM_RSP) ? miss_addr :
i_p_addr[send_index_to_bank[bank_id]];
// assign evicted_way_new[bank_id] = (state == SEND_MEM_REQ) ? way_used[bank_id] :
// (state == RECIV_MEM_RSP) ? evicted_way_old[bank_id] :
// 0;
wire[1:0] byte_select = bank_addr[1:0];
wire[TAG_SIZE_END:TAG_SIZE_START] cache_tag = bank_addr[ADDR_TAG_END:ADDR_TAG_START];
`ifdef SYN_FUNC
wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = 0;
wire[IND_SIZE_END:IND_SIZE_START] cache_index = 0;
`else
wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = bank_addr[ADDR_OFFSET_END:ADDR_OFFSET_START];
wire[IND_SIZE_END:IND_SIZE_START] cache_index = bank_addr[ADDR_IND_END:ADDR_IND_START];
`endif
wire normal_valid_in = valid_per_bank[bank_id];
wire use_valid_in = ((state == RECIV_MEM_RSP) && i_m_ready) ? 1'b1 :
((state == RECIV_MEM_RSP) && !i_m_ready) ? 1'b0 :
((state == SEND_MEM_REQ)) ? 1'b0 :
normal_valid_in;
VX_Cache_Bank #(
.CACHE_SIZE (CACHE_SIZE),
.CACHE_WAYS (CACHE_WAYS),
.CACHE_BLOCK (CACHE_BLOCK),
.CACHE_BANKS (CACHE_BANKS),
.LOG_NUM_BANKS (LOG_NUM_BANKS),
.NUM_REQ (NUM_REQ),
.LOG_NUM_REQ (LOG_NUM_REQ),
.NUM_IND (NUM_IND),
.CACHE_WAY_INDEX (CACHE_WAY_INDEX),
.NUM_WORDS_PER_BLOCK (NUM_WORDS_PER_BLOCK),
.OFFSET_SIZE_START (OFFSET_SIZE_START),
.OFFSET_SIZE_END (OFFSET_SIZE_END),
.TAG_SIZE_START (TAG_SIZE_START),
.TAG_SIZE_END (TAG_SIZE_END),
.IND_SIZE_START (IND_SIZE_START),
.IND_SIZE_END (IND_SIZE_END),
.ADDR_TAG_START (ADDR_TAG_START),
.ADDR_TAG_END (ADDR_TAG_END),
.ADDR_OFFSET_START (ADDR_OFFSET_START),
.ADDR_OFFSET_END (ADDR_OFFSET_END),
.ADDR_IND_START (ADDR_IND_START),
.ADDR_IND_END (ADDR_IND_END)
) bank_structure (
.clk (clk),
.rst (rst),
.state (state),
.valid_in (use_valid_in),
.actual_index (cache_index),
.o_tag (cache_tag),
.block_offset (cache_offset),
.writedata (i_p_writedata[send_index_to_bank[bank_id]]),
.read_or_write (i_p_read_or_write),
.i_p_mem_read (i_p_mem_read),
.i_p_mem_write (i_p_mem_write),
.byte_select (byte_select),
.hit (hit_per_bank[bank_id]),
.readdata (readdata_per_bank[bank_id]), // Data read
.eviction_addr (eviction_addr_per_bank[bank_id]),
.data_evicted (o_m_writedata[bank_id]),
.eviction_wb (eviction_wb[bank_id]), // Something needs to be written back
.fetched_writedata(i_m_readdata[bank_id]), // Data From memory
.evicted_way (global_way_to_evict)
);
end
endgenerate
// Mem Rsp
// Req to mem:
assign o_m_evict_addr = (eviction_addr_per_bank[0]) & MEM_ADDR_REQ_MASK; // Could be anything because tag+index are same
assign o_m_read_addr = miss_addr & MEM_ADDR_REQ_MASK;
assign o_m_valid = (state == SEND_MEM_REQ);
assign o_m_read_or_write = (state == SEND_MEM_REQ) && (|eviction_wb);
//end
endmodule

115
rtl/cache/VX_d_cache_encapsulate.v vendored
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@@ -1,115 +0,0 @@
`include "VX_define.v"
`define NUM_WORDS_PER_BLOCK 4
module VX_d_cache_encapsulate (
clk,
rst,
i_p_initial_request,
i_p_addr,
i_p_writedata,
i_p_read_or_write,
i_p_valid,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_writedata,
o_m_read_or_write,
o_m_valid,
i_m_readdata,
i_m_ready
);
parameter NUMBER_BANKS = 8;
//parameter cache_entry = 9;
input wire clk, rst;
input wire i_p_valid[`NT_M1:0];
input wire [31:0] i_p_addr[`NT_M1:0];
input wire i_p_initial_request;
input wire [31:0] i_p_writedata[`NT_M1:0];
input wire i_p_read_or_write;
input wire [31:0] i_m_readdata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0];
input wire i_m_ready;
output reg [31:0] o_p_readdata[`NT_M1:0];
output reg o_p_readdata_valid[`NT_M1:0] ;
output reg o_p_waitrequest;
output reg [31:0] o_m_addr;
output reg o_m_valid;
output reg [31:0] o_m_writedata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0];
output reg o_m_read_or_write;
// Inter
wire [`NT_M1:0] i_p_valid_inter;
wire [`NT_M1:0][31:0] i_p_addr_inter;
wire [`NT_M1:0][31:0] i_p_writedata_inter;
reg [`NT_M1:0][31:0] o_p_readdata_inter;
reg [`NT_M1:0] o_p_readdata_valid_inter;
reg[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_inter;
wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter;
genvar curr_thraed, curr_bank, curr_word;
generate
for (curr_thraed = 0; curr_thraed < `NT; curr_thraed = curr_thraed + 1) begin : threads
assign i_p_valid_inter[curr_thraed] = i_p_valid[curr_thraed];
assign i_p_addr_inter[curr_thraed] = i_p_addr[curr_thraed];
assign i_p_writedata_inter[curr_thraed] = i_p_writedata[curr_thraed];
assign o_p_readdata[curr_thraed] = o_p_readdata_inter[curr_thraed];
assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_inter[curr_thraed];
end
for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin : banks
for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : words
assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_inter[curr_bank][curr_word];
assign i_m_readdata_inter[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];
end
end
endgenerate
VX_d_cache dcache(
.clk (clk),
.rst (rst),
.i_p_valid (i_p_valid_inter),
.i_p_addr (i_p_addr_inter),
.i_p_initial_request(i_p_initial_request),
.i_p_writedata (i_p_writedata_inter),
.i_p_read_or_write (i_p_read_or_write),
.o_p_readdata (o_p_readdata_inter),
.o_p_readdata_valid (o_p_readdata_valid_inter),
.o_p_waitrequest (o_p_waitrequest),
.o_m_addr (o_m_addr),
.o_m_valid (o_m_valid),
.o_m_writedata (o_m_writedata_inter),
.o_m_read_or_write (o_m_read_or_write),
.i_m_readdata (i_m_readdata_inter),
.i_m_ready (i_m_ready)
);
endmodule

58
rtl/cache/VX_d_cache_tb.v vendored
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@@ -1,58 +0,0 @@
`include "VX_define.v"
`include "VX_d_cache.v"
module VX_d_cache_tb;
parameter NUMBER_BANKS = 8;
reg clk, reset, im_ready;
reg [`NT_M1:0] i_p_valid;
reg [`NT_M1:0][13:0] i_p_addr; // FIXME
reg i_p_initial_request;
reg [`NT_M1:0][31:0] i_p_writedata;
reg i_p_read_or_write; //, i_p_write;
reg [`NT_M1:0][31:0] o_p_readdata;
reg [`NT_M1:0] o_p_readdata_valid;
reg o_p_waitrequest;
reg [13:0] o_m_addr; // Only one address is sent out at a time to memory
reg o_m_valid;
reg [(NUMBER_BANKS * 32) - 1:0] o_m_writedata;
reg o_m_read_or_write; //, o_m_write;
reg [(NUMBER_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller
VX_d_cache d_cache(.clk(clk),
.rst(reset),
.i_p_initial_request(i_p_initial_request),
.i_p_addr(i_p_addr),
.i_p_writedata(i_p_writedata),
.i_p_read_or_write(i_p_read_or_write), // 0 = Read | 1 = Write
.i_p_valid(i_p_valid),
.o_p_readdata(o_p_readdata),
.o_p_readdata_valid(o_p_readdata_valid),
.o_p_waitrequest(o_p_waitrequest), // 0 = all threads done | 1 = Still threads that need to
.o_m_addr(o_m_addr),
.o_m_writedata(o_m_writedata),
.o_m_read_or_write(o_m_read_or_write), // 0 = Read | 1 = Write
.o_m_valid(o_m_valid),
.i_m_readdata(i_m_readdata),
.i_m_ready(im_ready)
//cnt_r,
//cnt_w,
//cnt_hit_r,
//cnt_hit_w
);
initial
begin
clk = 0;
reset = 0;
end
always
#5 clk = ! clk;
endmodule

24
rtl/cache/VX_generic_pe.v vendored
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@@ -1,24 +0,0 @@
module VX_generic_pe
#(
parameter N = 8
)
(
input wire[N-1:0] valids,
output reg[$clog2(N)-1:0] index,
output reg found
);
parameter my_secret = 0;
integer i;
always @(*) begin
index = 0;
found = 0;
for (i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
index = i[$clog2(N)-1:0];
found = 1;
end
end
end
endmodule

233
rtl/cache/cache_set.v vendored
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@@ -1,233 +0,0 @@
// To Do: Change way_id_out to an internal register which holds when in between access and finished.
// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
// Also make sure all possible output states are transmitted back to the bank correctly
// `include "VX_define.v"
module cache_set(clk,
rst,
// These next 4 are possible modes that the Set could be in, I am making them 4 different variables for indexing purposes
access, // First
find_evict,
write_from_mem,
idle,
// entry,
o_tag,
writedata,
//byte_en,
write,
//word_en,
//way_id_in,
//way_id_out,
readdata,
//wb_addr,
hit,
eviction_wb,
eviction_tag,
//eviction_data,
//modify,
miss
//valid_data
//read_miss
);
parameter cache_entry = 14;
parameter ways_per_set = 4;
input wire clk, rst;
input wire access;
input wire find_evict;
input wire write_from_mem;
input wire idle;
//input wire [cache_entry-1:0] entry;
input wire [1:0] o_tag;
input wire [31:0] writedata;
//input wire [3:0] byte_en;
input wire write; // 0 == False
//input wire [3:0] word_en;
//input wire read_miss;
//input wire [1:0] way_id_in;
//output reg [1:0] way_id_out;
output reg [31:0] readdata;
//output reg [3:0] hit;
output reg hit;
output reg miss;
output wire eviction_wb;
output wire [1:0] eviction_tag;
reg [31:0] eviction_data;
//output wire [22:0] wb_addr;
//output wire modify, valid_data;
//wire [2:0] i_tag;
//wire dirty;
//wire [24-cache_entry:0] write_tag_data;
// Table for one set
reg [2:0] counter; // Determines which to evict
reg valid [ways_per_set-1:0];
reg [1:0] tag [ways_per_set-1:0];
reg clean [ways_per_set-1:0];
reg [31:0] data [ways_per_set-1:0];
assign eviction_wb = miss && clean[counter[1:0]] != 1'b1 && valid[counter[1:0]] == 1'b1;
assign eviction_tag = tag[counter[1:0]];
//assign eviction_data = data[counter[1:0]];
//assign hit = valid_data && (o_tag == i_tag);
//assign modify = valid_data && (o_tag != i_tag) && dirty;
//assign miss = !valid_data || ((o_tag != i_tag) && !dirty);
//assign wb_addr = {i_tag, entry};
always @(posedge clk) begin
if (rst) begin
end
if (find_evict) begin
if (tag[0] == o_tag && valid[0]) begin
readdata <= data[0];
end else if (tag[1] == o_tag && valid[1]) begin
readdata <= data[1];
end else if (tag[2] == o_tag && valid[2]) begin
readdata <= data[2];
end else if (tag[3] == o_tag && valid[3]) begin
readdata <= data[3];
end
end else if (access) begin
//tag[`NT_M1:0] <= i_p_addr[`NT_M1:0][13:12];
counter <= ((counter + 1) ^ 3'b100); // Counter determining which to evict in the event of miss only increment when miss !!! NEED TO FIX LOGIC
// Hit in First Column
if (tag[0] == o_tag && valid[0]) begin
if (write == 1'b0) begin // if it is a read
if (clean[0] == 1'b1 ) begin
//hit <= 4'b0001;
hit <= 1'b1;
readdata <= data[0];
miss <= 1'b0;
end else begin
//hit <= 4'b0000; // SHOULD PROBABLY TRACK WHERE THIS MISS IS IN A DIFFERENT VARIABLE
hit <= 1'b0;
readdata <= 32'b0;
miss <= 1'b1;
end
end else if (write == 1'b1) begin
data[0] <= writedata;
clean[0] <= 1'b0;
//hit <= 4'b0001;
hit <= 1'b1;
end
end
// Hit in Second Column
else if (tag[1] == o_tag && valid[1]) begin
if (write == 1'b0) begin // if it is a read
if (clean[1] == 1'b1 ) begin
//hit <= 4'b0010;
hit <= 1'b1;
readdata <= data[1];
miss <= 1'b0;
end else begin
//hit <= 4'b0000;
hit <= 1'b0;
readdata <= 32'b0;
miss <= 1'b1;
end
end else if (write == 1'b1) begin
data[1] <= writedata;
clean[1] <= 1'b0;
//hit <= 4'b0010;
hit <= 1'b1;
end
end
// Hit in Third Column
else if (tag[2] == o_tag && valid[2]) begin
if (write == 1'b0) begin // if it is a read
if (clean[2] == 1'b1 ) begin
//hit <= 4'b0100;
hit <= 1'b1;
readdata <= data[2];
miss <= 1'b0;
end else begin
//hit <= 4'b0000;
hit <= 1'b0;
readdata <= 32'b0;
miss <= 1'b1;
end
end else if (write == 1'b1) begin
data[2] <= writedata;
clean[2] <= 1'b0;
//hit <= 4'b0100;
hit <= 1'b1;
end
end
// Hit in Fourth Column
else if (tag[3] == o_tag && valid[3]) begin
if (write == 1'b0) begin // if it is a read
if (clean[3] == 1'b1 ) begin
//hit <= 4'b1000;
hit <= 1'b1;
readdata <= data[3];
miss <= 1'b0;
end else begin
//hit <= 4'b0000;
hit <= 1'b0;
readdata <= 32'b0;
miss <= 1'b1;
end
end else if (write == 1'b1) begin
data[3] <= writedata;
clean[3] <= 1'b0;
//hit <= 4'b1000;
hit <= 1'b1;
end
end
// Miss
else begin
//way_id_out <= counter;
miss <= 1'b1;
if (write == 1'b0) begin // Read Miss
clean[counter[1:0]] <= 1'b1;
data[counter[1:0]] <= 32'h7FF; // FIX WITH ACTUAL MEMORY ACCESS
end else if (write == 1'b1) begin // Write Miss
clean[counter[1:0]] <= 1'b1;
data[counter[1:0]] <= writedata;
end
end
end
if (write_from_mem) begin
tag[counter[1:0]] <= o_tag;
valid[counter[1:0]] <= 1'b1;
hit <= 1'b1;
if (write == 1'b0) begin // Read Miss
clean[counter[1:0]] <= 1'b1;
data[counter[1:0]] <= 32'h7FF; // FIX WITH ACTUAL MEMORY ACCESS
end else if (write == 1'b1) begin // Write Miss
clean[counter[1:0]] <= 1'b0;
data[counter[1:0]] <= writedata;
end
end
if (idle) begin // Set "way" register equal to invalid value
hit <= 1'b1; // set to know it is ready
miss <= 1'b0;
readdata <= 32'hFFFFFFFF;
end
if (find_evict) begin // Keep "way" value the same !!!! Fix. Need to send back data with matching tag. Also need to ensure evicted data doesnt get lost
if (tag[3] == o_tag && valid[3]) begin
readdata <= data[3];
end else if (tag[1] == o_tag && valid[1]) begin
readdata <= data[1];
end else if (tag[2] == o_tag && valid[2]) begin
readdata <= data[2];
end else if (tag[0] == o_tag && valid[0]) begin
readdata <= data[0];
end else begin
readdata <= eviction_data;
end
hit <= 1'b1;
miss <= 1'b0;
end
counter <= ((counter + 1) ^ 3'b100); // Counter determining which to evict in the event of miss only increment when miss !!! NEED TO FIX LOGIC
eviction_data <= data[counter[1:0]];
end
endmodule

29
rtl/cache/d_cache_test_bench.cpp vendored
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@@ -1,29 +0,0 @@
#include "d_cache_test_bench.h"
//#define NUM_TESTS 46
int main(int argc, char **argv)
{
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
VX_d_cache v;
bool curr = v.simulate();
//if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
//if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
if ( curr) std::cerr << GREEN << "Test Passed: " << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << std::endl;
return 0;
}

355
rtl/cache/d_cache_test_bench.h vendored
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@@ -1,355 +0,0 @@
// C++ libraries
#include <utility>
#include <iostream>
#include <map>
#include <iterator>
#include <iomanip>
#include <fstream>
#include <unistd.h>
#include <vector>
#include <math.h>
#include <algorithm>
#include "VX_define.h"
#include "VVX_d_cache_encapsulate.h"
#include "verilated.h"
#include "d_cache_test_bench_debug.h"
#ifdef VCD_OUTPUT
#include <verilated_vcd_c.h>
#endif
// void set_Index (auto & var, int index, int size, auto val)
// {
// int real_shift
// }
class VX_d_cache
{
public:
VX_d_cache();
~VX_d_cache();
bool simulate();
bool operation(int, bool);
VVX_d_cache_encapsulate * vx_d_cache_;
long int curr_cycle;
int stats_total_cycles = 0;
int stats_dram_accesses = 0;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
};
VX_d_cache::VX_d_cache() : curr_cycle(0), stats_total_cycles(0), stats_dram_accesses(0)
{
this->vx_d_cache_ = new VVX_d_cache_encapsulate;
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
this->vx_d_cache_->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
//this->results.open("../results.txt");
}
VX_d_cache::~VX_d_cache()
{
delete this->vx_d_cache_;
#ifdef VCD_OUTPUT
m_trace->close();
#endif
}
bool VX_d_cache::operation(int counter_value, bool do_op) {
if (do_op) {
vx_d_cache_->i_p_initial_request = 1;
} else {
vx_d_cache_->i_p_initial_request = 0;
}
if (counter_value == 0 && do_op) { // Write to bank 1-4 at index 64
vx_d_cache_->i_p_initial_request = 1;
vx_d_cache_->i_p_read_or_write = 1;
vx_d_cache_->i_m_ready = 0;
for (int j = 0; j < NT; j++) {
vx_d_cache_->i_p_valid[j] = 1;
vx_d_cache_->i_p_writedata[j] = 0x7f6f8f6f;
vx_d_cache_->i_m_readdata[j][0] = 1;
if (j == 0) {
vx_d_cache_->i_p_addr[0] = 0x30001004; // bank 1
} else if (j == 1) {
vx_d_cache_->i_p_addr[1] = 0x30001008; // bank 2
} else if (j == 2) {
vx_d_cache_->i_p_addr[2] = 0x3000100c; // bank 3
} else {
vx_d_cache_->i_p_addr[3] = 0x30010010; // bank 4 -- This is serviced 1st, then the other 3 banks are at once
}
}
} else if (counter_value == 1 && do_op) { // Write to bank 4-7 at index 108
vx_d_cache_->i_p_initial_request = 1;
vx_d_cache_->i_p_read_or_write = 1;
vx_d_cache_->i_m_ready = 0;
for (int j = 0; j < NT; j++) {
vx_d_cache_->i_p_valid[j] = 1;
vx_d_cache_->i_p_writedata[j] = 0xd1d2d2d3;
vx_d_cache_->i_m_readdata[j][0] = 1;
if (j == 0) {
vx_d_cache_->i_p_addr[0] = 0x30001c14; // bank 5
} else if (j == 1) {
vx_d_cache_->i_p_addr[1] = 0x30001c18; // bank 6
} else if (j == 2) {
vx_d_cache_->i_p_addr[2] = 0x30001c1c; // bank 7
} else {
vx_d_cache_->i_p_addr[3] = 0x30001c10; // bank 4
}
}
} else if (counter_value == 2 && do_op) { // Read from bank 1-4 at those indexes
for (int j = 0; j < NT; j++) {
vx_d_cache_->i_p_initial_request = 1;
vx_d_cache_->i_p_read_or_write = 0;
vx_d_cache_->i_m_ready = 0;
for (int j = 0; j < NT; j++) {
vx_d_cache_->i_p_valid[j] = 1;
vx_d_cache_->i_p_writedata[j] = 0x23232332;
vx_d_cache_->i_m_readdata[j][0] = 1;
if (j == 0) {
vx_d_cache_->i_p_addr[0] = 0x30001004; // bank 1
} else if (j == 1) {
vx_d_cache_->i_p_addr[1] = 0x30001c18; // bank 5
} else if (j == 2) {
vx_d_cache_->i_p_addr[2] = 0x3000100c; // bank 3
} else {
vx_d_cache_->i_p_addr[3] = 0x30001c1c;; // bank 7
}
}
}
} else if (counter_value == 3 && do_op) { // Write to Bank 1-5 (evictions will need to take place)
vx_d_cache_->i_p_initial_request = 1;
vx_d_cache_->i_p_read_or_write = 1;
vx_d_cache_->i_m_ready = 0;
for (int j = 0; j < NT; j++) {
vx_d_cache_->i_p_valid[j] = 1;
vx_d_cache_->i_m_readdata[j][0] = 1;
if (j == 0) {
vx_d_cache_->i_p_addr[0] = 0x20001004; // bank 1
vx_d_cache_->i_p_writedata[j] = 0xaaaabbb0;
} else if (j == 1) {
vx_d_cache_->i_p_addr[1] = 0x20001008; // bank 2
vx_d_cache_->i_p_writedata[j] = 0xaaaabbb1;
} else if (j == 2) {
vx_d_cache_->i_p_addr[2] = 0x2000100c; // bank 3
vx_d_cache_->i_p_writedata[j] = 0xaaaabbb2;
} else {
vx_d_cache_->i_p_addr[3] = 0x20001c14; // bank 5
vx_d_cache_->i_p_writedata[j] = 0xaaaabbb3;
}
}
} else if (counter_value == 4 && do_op) { // Read from addresses that were just overwritten above ^^^
vx_d_cache_->i_p_initial_request = 1;
vx_d_cache_->i_p_read_or_write = 0;
vx_d_cache_->i_m_ready = 0;
for (int j = 0; j < NT; j++) {
vx_d_cache_->i_p_valid[j] = 1;
vx_d_cache_->i_p_writedata[j] = 0x23232332;
vx_d_cache_->i_m_readdata[j][0] = 1;
if (j == 0) {
vx_d_cache_->i_p_addr[0] = 0x20001004; // bank 1
} else if (j == 1) {
vx_d_cache_->i_p_addr[1] = 0x20001008; // bank 2
} else if (j == 2) {
vx_d_cache_->i_p_addr[2] = 0x2000100c; // bank 3
} else {
vx_d_cache_->i_p_addr[3] = 0x20001c14; // bank 5
}
}
}
/* These will check writing multiple threads writing to the same block
} else if (counter_value == 3 && do_op) { // Write to Bank 0
vx_d_cache_->i_p_initial_request = 1;
vx_d_cache_->i_p_read_or_write = 1;
vx_d_cache_->i_m_ready = 0;
for (int j = 0; j < NT; j++) {
vx_d_cache_->i_p_valid[j] = 1;
vx_d_cache_->i_m_readdata[j][0] = 1;
if (j == 0) {
vx_d_cache_->i_p_addr[0] = 0x30001f00; // bank 0
vx_d_cache_->i_p_writedata[j] = 0xaaaabbb0;
} else if (j == 1) {
vx_d_cache_->i_p_addr[1] = 0x30001c00; // bank 0
vx_d_cache_->i_p_writedata[j] = 0xaaaabbb1;
} else if (j == 2) {
vx_d_cache_->i_p_addr[2] = 0x30001a00; // bank 0
vx_d_cache_->i_p_writedata[j] = 0xaaaabbb2;
} else {
vx_d_cache_->i_p_addr[3] = 0x30001904; // bank 1
vx_d_cache_->i_p_writedata[j] = 0xaaaabbb3;
}
}
} else if (counter_value == 4 && do_op) { // Read from Bank 0
vx_d_cache_->i_p_initial_request = 1;
vx_d_cache_->i_p_read_or_write = 0;
vx_d_cache_->i_m_ready = 0;
for (int j = 0; j < NT; j++) {
vx_d_cache_->i_p_valid[j] = 1;
vx_d_cache_->i_p_writedata[j] = 0x23232332;
vx_d_cache_->i_m_readdata[j][0] = 1;
if (j == 0) {
vx_d_cache_->i_p_addr[0] = 0x30001f00; // bank 0
} else if (j == 1) {
vx_d_cache_->i_p_addr[1] = 0x30001c00; // bank 0
} else if (j == 2) {
vx_d_cache_->i_p_addr[2] = 0x30001a00; // bank 0
} else {
vx_d_cache_->i_p_addr[3] = 0x30001904; // bank 1
}
}
}
*/
// Handle Memory Accesses
unsigned int read_data_from_mem = 0x1111 + counter_value + this->stats_total_cycles;
if (vx_d_cache_->o_m_valid) {
this->stats_dram_accesses = this->stats_dram_accesses + 1; // (assuming memory access takes 20 cycles)
this->stats_total_cycles += 1;
vx_d_cache_->clk = 0;
vx_d_cache_->eval();
#ifdef VCD_OUTPUT
m_trace->dump(2*this->stats_total_cycles);
#endif
vx_d_cache_->clk = 1;
vx_d_cache_->eval();
#ifdef VCD_OUTPUT
m_trace->dump((2*this->stats_total_cycles)+1);
#endif
vx_d_cache_->i_m_ready = 1;
for (int j1 = 0; j1 < 8; j1++) {
for (int j2 = 0; j2 < 4; j2++) {
vx_d_cache_->i_m_readdata[j1][j2] = read_data_from_mem;
}
}
} else {
vx_d_cache_->i_m_ready = 0;
}
if (vx_d_cache_->o_p_waitrequest == 0) {
return true;
} else {
return false;
}
}
bool VX_d_cache::simulate()
{
// this->instruction_file_name = file_to_simulate;
// this->results << "\n****************\t" << file_to_simulate << "\t****************\n";
// this->ProcessFile();
// auto start_time = std::chrono::high_resolution_clock::now();
//static bool stop = false;
//static int counter = 0;
//counter = 0;
//stop = false;
// auto start_time = clock();
vx_d_cache_->clk = 0;
vx_d_cache_->rst = 1;
//vortex->eval();
//counter = 0;
vx_d_cache_->rst = 0;
bool cont = false;
bool out_operation = false;
bool do_operation = true;
int other_counter = 0;
//while (this->stop && ((other_counter < 5)))
while (other_counter < 5)
{
// std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
// istop = ibus_driver();
// dstop = !dbus_driver();
vx_d_cache_->clk = 1;
vx_d_cache_->eval();
#ifdef VCD_OUTPUT
m_trace->dump(2*this->stats_total_cycles);
#endif
//vortex->eval();
//dstop = !dbus_driver();
out_operation = operation(other_counter, do_operation);
vx_d_cache_->clk = 0;
vx_d_cache_->eval();
#ifdef VCD_OUTPUT
m_trace->dump((2*this->stats_total_cycles)+1);
#endif
//vortex->eval();
/*
// stop = istop && dstop;
stop = vortex->out_ebreak;
if (stop || cont)
{
cont = true;
counter++;
} else
{
counter = 0;
}
*/
if (out_operation) {
other_counter++;
do_operation = true;
} else {
do_operation = false;
}
++(this->stats_total_cycles);
if (this->stats_total_cycles > 5000) {
break;
}
}
std::cerr << "New Total Cycles: " << (this->stats_total_cycles + (this->stats_dram_accesses * 20)) << "\n";
//uint32_t status;
//ram.getWord(0, &status);
//this->print_stats();
return (true);
}

1
rtl/cache/d_cache_test_bench_debug.h vendored
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@@ -1 +0,0 @@
#define VCD_OUTPUT

70
rtl/cache/quartus/Makefile vendored
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@@ -1,70 +0,0 @@
PROJECT = VX_d_cache
TOP_LEVEL_ENTITY = VX_d_cache
SRC_FILE = ../VX_d_cache.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
# Executable Configuration
SYN_ARGS = --parallel --read_settings_files=on
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
ASM_ARGS =
STA_ARGS = --do_report_timing
# Build targets
all: $(PROJECT).sta.rpt
syn: $(PROJECT).syn.rpt
fit: $(PROJECT).fit.rpt
asm: $(PROJECT).asm.rpt
sta: $(PROJECT).sta.rpt
smart: smart.log
# Target implementations
STAMP = echo done >
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
quartus_sta $(PROJECT) $(STA_ARGS)
smart.log: $(PROJECT_FILES)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization
$(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../;../../"
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean:
rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

1
rtl/cache/quartus/project.sdc vendored
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@@ -1 +0,0 @@
create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

41
rtl/cache/quartus/project.tcl vendored
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@@ -1,41 +0,0 @@
load_package flow
package require cmdline
set options { \
{ "project.arg" "" "Project name" } \
{ "family.arg" "" "Device family name" } \
{ "device.arg" "" "Device name" } \
{ "top.arg" "" "Top level module" } \
{ "sdc.arg" "" "Timing Design Constraints file" } \
{ "src.arg" "" "Verilog source file" } \
{ "inc.arg" "." "Include path" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name VERILOG_FILE $opts(src)
set_global_assignment -name SEARCH_PATH $opts(inc)
set_global_assignment -name SDC_FILE $opts(sdc)
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
proc make_all_pins_virtual {} {
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
}
make_all_pins_virtual
project_close

138
rtl/compat/VX_divide.v
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@@ -1,138 +0,0 @@
module VX_divide
#(
parameter WIDTHN=1,
parameter WIDTHD=1,
parameter NREP="UNSIGNED",
parameter DREP="UNSIGNED",
parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
parameter PIPELINE=0
)
(
input clock, aclr, clken,
input [WIDTHN-1:0] numer,
input [WIDTHD-1:0] denom,
output reg [WIDTHN-1:0] quotient,
output reg [WIDTHD-1:0] remainder
);
// synthesis read_comments_as_HDL on
// localparam IMPL = "quartus";
// synthesis read_comments_as_HDL off
// altera translate_off
localparam IMPL="fallback";
// altera translate_on
generate
if (NREP != DREP) begin
different_nrep_drep_not_yet_supported non_existing_module();
end
if (IMPL == "quartus") begin
localparam lpm_speed=SPEED == "HIGHEST" ? 9:5;
lpm_divide#(
.LPM_WIDTHN(WIDTHN),
.LPM_WIDTHD(WIDTHD),
.LPM_NREPRESENTATION(NREP),
.LPM_DREPRESENTATION(DREP),
.LPM_PIPELINE(PIPELINE),
.LPM_REMAINDERPOSITIVE("FALSE"), // emulate verilog % operator
.MAXIMIZE_SPEED(lpm_speed)
) quartus_divider(
.clock(clock),
.aclr(aclr),
.clken(clken),
.numer(numer),
.denom(denom),
.quotient(quotient),
.remain(remainder)
);
end
else begin
wire [WIDTHN-1:0] numer_pipe_end;
wire [WIDTHD-1:0] denom_pipe_end;
if (PIPELINE == 0) begin
assign numer_pipe_end = numer;
assign denom_pipe_end = denom;
end else begin
reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
genvar pipe_stage;
for (pipe_stage = 0; pipe_stage < PIPELINE-1; pipe_stage = pipe_stage+1) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
numer_pipe[pipe_stage+1] <= 0;
denom_pipe[pipe_stage+1] <= 0;
end
else if (clken) begin
numer_pipe[pipe_stage+1] <= numer_pipe[pipe_stage];
denom_pipe[pipe_stage+1] <= denom_pipe[pipe_stage];
end
end
end
always @(posedge clock or posedge aclr) begin
if (aclr) begin
numer_pipe[0] <= 0;
denom_pipe[0] <= 0;
end
else if (clken) begin
numer_pipe[0] <= numer;
denom_pipe[0] <= denom;
end
end
assign numer_pipe_end = numer_pipe[PIPELINE-1];
assign denom_pipe_end = denom_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
if (NREP == "SIGNED") begin
/*VX_divide_internal_signed #(
.WIDTHN,
.WIDTHD
)div(
.numer(numer_pipe_end),
.denom(denom_pipe_end),
.quotient,
.remainder
);*/
always @(*) begin
if (denom_pipe_end == 0) begin
quotient = 32'hffffffff;
remainder = numer_pipe_end;
end
else if (denom_pipe_end == 32'hffffffff && numer_pipe_end == 32'h80000000) begin
// this edge case kills verilator in some cases by causing a division
// overflow exception. INT_MIN / -1 (on x86)
quotient = 0;
remainder = 0;
end
else begin
quotient = $signed($signed(numer_pipe_end)/$signed(denom_pipe_end));
remainder = $signed($signed(numer_pipe_end)%$signed(denom_pipe_end));
end
end
end
else begin
assign quotient = (denom_pipe_end == 0) ? 32'hffffffff : numer_pipe_end/denom_pipe_end;
assign remainder = (denom_pipe_end == 0) ? numer_pipe_end : numer_pipe_end%denom_pipe_end;
end
end
endgenerate
endmodule : VX_divide

125
rtl/compat/VX_mult.v
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@@ -1,125 +0,0 @@
module VX_mult
#(
parameter WIDTHA=1,
parameter WIDTHB=1,
parameter WIDTHP=1,
parameter REP="UNSIGNED",
parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
parameter PIPELINE=0,
parameter FORCE_LE="NO"
)
(
input clock, aclr, clken,
input [WIDTHA-1:0] dataa,
input [WIDTHB-1:0] datab,
output reg [WIDTHP-1:0] result
);
// synthesis read_comments_as_HDL on
// localparam IMPL = "quartus";
// synthesis read_comments_as_HDL off
// altera translate_off
localparam IMPL="fallback";
// altera translate_on
generate
if (IMPL == "quartus") begin
localparam lpm_speed=SPEED == "HIGHEST" ? 10:5;
if (FORCE_LE == "YES") begin
lpm_mult#(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult(
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
else begin
lpm_mult#(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult(
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
end
else begin
wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end;
if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab;
end else begin
reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
genvar pipe_stage;
for (pipe_stage = 0; pipe_stage < PIPELINE-1; pipe_stage = pipe_stage+1) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[pipe_stage+1] <= 0;
datab_pipe[pipe_stage+1] <= 0;
end
else if (clken) begin
dataa_pipe[pipe_stage+1] <= dataa_pipe[pipe_stage];
datab_pipe[pipe_stage+1] <= datab_pipe[pipe_stage];
end
end
end
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[0] <= 0;
datab_pipe[0] <= 0;
end
else if (clken) begin
dataa_pipe[0] <= dataa;
datab_pipe[0] <= datab;
end
end
assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
assign datab_pipe_end = datab_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
if (REP == "SIGNED") begin
assign result = $signed($signed(dataa_pipe_end)*$signed(datab_pipe_end));
end
else begin
assign result = dataa_pipe_end*datab_pipe_end;
end
end
endgenerate
endmodule: VX_mult

160
rtl/compat/VX_tb_divide.sv
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@@ -1,160 +0,0 @@
`timescale 1ns/1ps
module VX_tb_divide();
`ifdef TRACE
initial
begin
$dumpfile("trace.vcd");
$dumpvars(0,test);
end
`endif
reg clk;
reg rst;
reg [31:0] numer, denom;
wire [31:0] o_div[0:7], o_rem[0:7];
genvar i;
generate
for (i = 0; i < 8; i = i+1) begin : div_loop
VX_divide#(
.WIDTHN(32),
.WIDTHD(32),
.PIPELINE(i)
) div(
.clock(clk),
.aclr(rst),
.clken(1'b1),
.numer(numer),
.denom(denom),
.quotient(o_div[i]),
.remainder(o_rem[i])
);
end
endgenerate
initial begin
clk = 0; rst = 0;
numer = 56;
denom = 11;
$display("56 / 11 #0");
if (o_div[0] != 5 || o_rem[0] != 1) begin
$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
$display("expected 5,1 EXITING");
$finish();
end
if (o_div[1] != 1'bx || o_rem[1] != 1'bx) begin
$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
$display("expected x,x EXITING");
$finish();
end
if (o_div[2] != 1'bx || o_rem[2] != 1'bx) begin
$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
$display("expected x,x EXITING");
$finish();
end
if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
$display("expected x,x EXITING");
$finish();
end
#2;
$display("56 / 11 #2");
if (o_div[0] != 5 || o_rem[0] != 1) begin
$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
$display("expected 5,1, EXITING");
$finish();
end
if (o_div[1] != 5 || o_rem[1] != 1) begin
$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
$display("expected 5,1 EXITING");
$finish();
end
if (o_div[2] != 1'bx || o_rem[2] != 1'bx) begin
$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
$display("expected x,x EXITING");
$finish();
end
if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
$display("expected x,x EXITING");
$finish();
end
#2;
$display("56 / 11 #4");
if (o_div[0] != 5 || o_rem[0] != 1) begin
$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
$display("expected 5,1 EXITING");
$finish();
end
if (o_div[1] != 5 || o_rem[1] != 1) begin
$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
$display("expected 5,1 EXITING");
$finish();
end
if (o_div[2] != 5 || o_rem[2] != 1) begin
$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
$display("expected 5,1 EXITING");
$finish();
end
if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
$display("expected x,x EXITING");
$finish();
end
#2;
$display("56 / 11 #6");
if (o_div[0] != 5 || o_rem[0] != 1) begin
$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
$display("expected 5,1 EXITING");
$finish();
end
if (o_div[1] != 5 || o_rem[1] != 1) begin
$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
$display("expected 5,1 EXITING");
$finish();
end
if (o_div[2] != 5 || o_rem[2] != 1) begin
$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
$display("expected 5,1 EXITING");
$finish();
end
if (o_div[3] != 5 || o_rem[3] != 1) begin
$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
$display("expected 5,1 EXITING");
$finish();
end
$display("PASS");
$finish();
end
always #1
clk = ~clk;
endmodule: VX_tb_divide

2
rtl/configs/.gitignore vendored
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@@ -1,2 +0,0 @@
*.v
*.sh

0
rtl/configs/.gitkeep
View File

139
rtl/gen_config.py
View File

@@ -1,139 +0,0 @@
#!/usr/bin/env python3
# coding=utf-8
from __future__ import print_function
import os
import os.path as path
import re
import argparse
from datetime import datetime
rtl_root = path.dirname(path.realpath(__file__))
defines = {}
for k, v in os.environ.items():
if k.upper().startswith('V_'):
defines[k[2:]] = v
print('Custom params:', ', '.join(['='.join(x) for x in defines.items()]))
parser = argparse.ArgumentParser()
parser.add_argument('--outc', default='none', help='Output C header')
parser.add_argument('--outv', default='none', help='Output Verilog header')
parser.add_argument('--rtl_locations', action='store_true', help='use outc and outv for rtl and rtl/simulate')
args = parser.parse_args()
if args.rtl_locations:
args.outc = path.join(rtl_root, 'simulate/VX_define.h')
args.outv = path.join(rtl_root, 'VX_define_synth.v')
if args.outc == 'none' and args.outv == 'none':
print('Warning: not emitting any files. Specify arguments')
if args.outv != 'none':
with open(args.outv, 'w') as f:
print('''
// auto-generated by gen_config.py. DO NOT EDIT
// Generated at {date}
`ifndef VX_DEFINE_SYNTH
`define VX_DEFINE_SYNTH
'''[1:].format(date=datetime.now()), file=f)
for k, v in defines.items():
print('`define {} {}'.format(k, v), file=f)
print('\n`endif', file=f)
if args.outc != 'none':
with open(args.outc, 'w') as f:
print('''
// auto-generated by gen_config.py. DO NOT EDIT
// Generated at {date}
#ifndef VX_DEFINE_SYNTH
#define VX_DEFINE_SYNTH
'''[1:].format(date=datetime.now()), file=f)
for k, v in defines.items():
print('#define {} {}'.format(k, v), file=f)
print('\n#endif', file=f)
translation_rules = [
(re.compile(r'^$'), r''),
(re.compile(r'^( *)`ifndef ([^ ]+)$'), r'\1#ifndef \2'),
(re.compile(r'^( *)`define ([^ ]+)$'), r'\1#define \2'),
# (re.compile(r'^( *)`include "\./VX_define_synth\.v"$'), r'\1#include "VX_define_synth.h"'),
(re.compile(r'^( *)`include "\./VX_define_synth\.v"$'), r''),
(re.compile(r'^( *)`define ([^ ]+) (.+)$'), r'\1#define \2 \3'),
(re.compile(r'^( *)`endif$'), r'\1#endif'),
(re.compile(r'^( *)// (.*)$'), r'\1// \2'),
]
post_rules = [
(re.compile(r"\d+'d(\d+)"), r'\1'),
# non-standard C but supported by GCC and Clang
(re.compile(r"\d+'b([01]+)"), r'0b\1'),
(re.compile(r"\d+'h([\da-fA-F]+)"), r'0x\1'),
# fix macro references (does not support escaped identifiers §5.6.1)
(re.compile(r"`([A-Za-z_][$_0-9A-Za-z]*)"), r'\1'),
]
def post_process_line(line):
for pat, repl in post_rules:
line = pat.sub(repl, line)
return line
in_expansion = False
if args.outc != 'none':
with open(args.outc, 'a') as f:
print('''
// auto-generated by gen_config.py. DO NOT EDIT
// Generated at {date}
// Translated from VX_define.v:
'''[1:].format(date=datetime.now()), file=f)
with open(path.join(rtl_root, 'VX_define.v'), 'r') as r:
for line in r:
if in_expansion:
f.write(post_process_line(line))
if not line.strip().endswith('\\'):
in_expansion = False
else:
for pat, repl in translation_rules:
if pat.match(line):
if line.strip().endswith('\\'):
in_expansion = True
f.write(post_process_line(pat.sub(repl, line)))
break
else:
raise ValueError('failed to find rule for: ' + line)
print('''
// Misc
#define THREADS_PER_WARP NT
#define WARPS_PER_CORE NW
#define NUMBER_WI (NW * NT * NUMBER_CORES_PER_CLUSTER * NUMBER_CLUSTERS)
// legacy
#define TOTAL_THREADS NUMBER_WI
#define TOTAL_WARPS (NW * NUMBER_CORES_PER_CLUSTER * NUMBER_CLUSTERS)
// COLORS
#define GREEN "\\033[32m"
#define RED "\\033[31m"
#define DEFAULT "\\033[39m"
'''[1:], file=f)

48
rtl/gen_synth_configs.py
View File

@@ -1,48 +0,0 @@
#!/usr/bin/env python3
import os
import glob
config_location = 'configs'
name_template = '{clusters}cl-{cores}c-{warps}w-{threads}t-{l2}Kl2-{dcache}Kd-{icache}Ki{name_suffix}.sh'
template = """
export V_NT={threads}
export V_NW={warps}
export V_NUMBER_CORES_PER_CLUSTER={cores}
export V_NUMBER_CLUSTERS={clusters}
export V_DCACHE_SIZE_BYTES={dcachek}
export V_ICACHE_SIZE_BYTES={icachek}
# L2 Cache size
export V_LLCACHE_SIZE_BYTES={l2k}
{codegen}
"""
# cluster, cores, warps, threads, l2, dcache, icache
configs = [
(1, 2, 8, 4, 8, 4, 1),
(1, 2, 8, 8, 8, 4, 1),
(1, 2, 8, 8, 16, 8, 1),
(1, 4, 8, 8, 16, 4, 1),
(1, 4, 8, 8, 16, 8, 1),
(1, 4, 16, 8, 16, 8, 1),
(2, 4, 8, 4, 8, 4, 1),
(2, 4, 8, 8, 16, 8, 1),
]
files = glob.glob(config_location + '/*.sh')
for f in files:
os.remove(f)
for clusters, cores, warps, threads, l2, dcache, icache in configs:
l2k, dcachek, icachek = 1024 * l2, 1024 * dcache, 1024 * icache
name_suffix = ''
with open(config_location + '/' + name_template.format(**locals()), 'w') as f:
codegen = ''
f.write(template.format(**locals()))

18
rtl/interfaces/VX_branch_response_inter.v
View File

@@ -1,18 +0,0 @@
`include "../VX_define.v"
`ifndef VX_BRANCH_RSP
`define VX_BRANCH_RSP
interface VX_branch_response_inter ();
wire valid_branch;
wire branch_dir;
wire[31:0] branch_dest;
wire[`NW_M1:0] branch_warp_num;
endinterface
`endif

24
rtl/interfaces/VX_csr_req_inter.v
View File

@@ -1,24 +0,0 @@
`include "../VX_define.v"
`ifndef VX_CSR_REQ
`define VX_CSR_REQ
interface VX_csr_req_inter ();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[4:0] rd;
wire[1:0] wb;
wire[4:0] alu_op;
wire is_csr;
wire[11:0] csr_address;
wire csr_immed;
wire[31:0] csr_mask;
endinterface
`endif

21
rtl/interfaces/VX_csr_wb_inter.v
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@@ -1,21 +0,0 @@
`include "../VX_define.v"
`ifndef VX_CSR_WB_REQ
`define VX_CSR_WB_REQ
interface VX_csr_wb_inter ();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[4:0] rd;
wire[1:0] wb;
wire[`NT_M1:0][31:0] csr_result;
endinterface
`endif

19
rtl/interfaces/VX_dcache_request_inter.v
View File

@@ -1,19 +0,0 @@
`include "../VX_define.v"
`ifndef VX_DCACHE_REQ
`define VX_DCACHE_REQ
interface VX_dcache_request_inter ();
wire[`NT_M1:0][31:0] out_cache_driver_in_address;
wire[2:0] out_cache_driver_in_mem_read;
wire[2:0] out_cache_driver_in_mem_write;
wire[`NT_M1:0] out_cache_driver_in_valid;
wire[`NT_M1:0][31:0] out_cache_driver_in_data;
endinterface
`endif

16
rtl/interfaces/VX_dcache_response_inter.v
View File

@@ -1,16 +0,0 @@
`include "../VX_define.v"
`ifndef VX_DCACHE_RSP
`define VX_DCACHE_RSP
interface VX_dcache_response_inter ();
wire[`NT_M1:0][31:0] in_cache_driver_out_data;
wire delay;
endinterface
`endif

27
rtl/interfaces/VX_dram_req_rsp_inter.v
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@@ -1,27 +0,0 @@
`include "../VX_define.v"
`ifndef VX_DRAM_REQ_RSP_INTER
`define VX_DRAM_REQ_RSP_INTER
interface VX_dram_req_rsp_inter #(
parameter NUMBER_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4) ();
// Req
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
// Rsp
wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;
endinterface
`endif

51
rtl/interfaces/VX_exec_unit_req_inter.v
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@@ -1,51 +0,0 @@
`include "../VX_define.v"
`ifndef VX_EXE_UNIT_REQ_INTER
`define VX_EXE_UNIT_REQ_INTER
interface VX_exec_unit_req_inter ();
// Meta
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[31:0] curr_PC;
wire[31:0] PC_next;
// Write Back Info
wire[4:0] rd;
wire[1:0] wb;
// Data and alu op
wire[`NT_M1:0][31:0] a_reg_data;
wire[`NT_M1:0][31:0] b_reg_data;
wire[4:0] alu_op;
wire[4:0] rs1;
wire[4:0] rs2;
wire rs2_src;
wire[31:0] itype_immed;
wire[19:0] upper_immed;
// Branch type
wire[2:0] branch_type;
// Jal info
wire jalQual;
wire jal;
wire[31:0] jal_offset;
/* verilator lint_off UNUSED */
wire ebreak;
wire wspawn;
/* verilator lint_on UNUSED */
// CSR info
wire is_csr;
wire[11:0] csr_address;
wire csr_immed;
wire[31:0] csr_mask;
endinterface
`endif

46
rtl/interfaces/VX_frE_to_bckE_req_inter.v
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@@ -1,46 +0,0 @@
`include "VX_define.v"
`ifndef VX_FrE_to_BE_INTER
`define VX_FrE_to_BE_INTER
interface VX_frE_to_bckE_req_inter ();
wire[11:0] csr_address;
wire is_csr;
wire csr_immed;
wire[31:0] csr_mask;
wire[4:0] rd;
wire[4:0] rs1;
wire[4:0] rs2;
wire[4:0] alu_op;
wire[1:0] wb;
wire rs2_src;
wire[31:0] itype_immed;
wire[2:0] mem_read;
wire[2:0] mem_write;
wire[2:0] branch_type;
wire[19:0] upper_immed;
wire[31:0] curr_PC;
/* verilator lint_off UNUSED */
wire ebreak;
/* verilator lint_on UNUSED */
wire jalQual;
wire jal;
wire[31:0] jal_offset;
wire[31:0] PC_next;
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
// GPGPU stuff
wire is_wspawn;
wire is_tmc;
wire is_split;
wire is_barrier;
endinterface
`endif

18
rtl/interfaces/VX_gpr_clone_inter.v
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@@ -1,18 +0,0 @@
`include "../VX_define.v"
`ifndef VX_GPR_CLONE_INTER
`define VX_GPR_CLONE_INTER
interface VX_gpr_clone_inter ();
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_M1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface
`endif

14
rtl/interfaces/VX_gpr_data_inter.v
View File

@@ -1,14 +0,0 @@
`include "../VX_define.v"
`ifndef VX_gpr_data_INTER
`define VX_gpr_data_INTER
interface VX_gpr_data_inter ();
wire[`NT_M1:0][31:0] a_reg_data;
wire[`NT_M1:0][31:0] b_reg_data;
endinterface
`endif

14
rtl/interfaces/VX_gpr_jal_inter.v
View File

@@ -1,14 +0,0 @@
`include "../VX_define.v"
`ifndef VX_GPR_JAL_INTER
`define VX_GPR_JAL_INTER
interface VX_gpr_jal_inter ();
wire is_jal;
wire[31:0] curr_PC;
endinterface
`endif

17
rtl/interfaces/VX_gpr_read_inter.v
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@@ -1,17 +0,0 @@
`include "../VX_define.v"
`ifndef VX_GPR_READ
`define VX_GPR_READ
interface VX_gpr_read_inter ();
wire[4:0] rs1;
wire[4:0] rs2;
wire[`NW_M1:0] warp_num;
endinterface
`endif

18
rtl/interfaces/VX_gpr_wspawn_inter.v
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@@ -1,18 +0,0 @@
`include "../VX_define.v"
`ifndef VX_GPR_WSPAWN_INTER
`define VX_GPR_WSPAWN_INTER
interface VX_gpr_wspawn_inter ();
/* verilator lint_off UNUSED */
wire is_wspawn;
wire[`NW_M1:0] which_wspawn;
// wire[`NW_M1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface
`endif

37
rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
View File

@@ -1,37 +0,0 @@
`include "../VX_cache/VX_cache_config.v"
`ifndef VX_GPU_DRAM_DCACHE_REQ
`define VX_GPU_DRAM_DCACHE_REQ
interface VX_gpu_dcache_dram_req_inter
#(
parameter BANK_LINE_SIZE_WORDS = 2
)
();
// DRAM Request
wire dram_req;
wire dram_req_write;
wire dram_req_read;
wire [31:0] dram_req_addr;
wire [31:0] dram_req_size;
wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_req_data;
// Snoop
wire dram_because_of_snp;
wire dram_snp_full;
// DRAM Cache can't accept response
wire dram_fill_accept;
// DRAM Cache can't accept request
wire dram_req_delay;
endinterface
`endif

23
rtl/interfaces/VX_gpu_dcache_dram_res_inter.v
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@@ -1,23 +0,0 @@
`include "../VX_cache/VX_cache_config.v"
`ifndef VX_GPU_DRAM_DCACHE_RES
`define VX_GPU_DRAM_DCACHE_RES
interface VX_gpu_dcache_dram_res_inter
#(
parameter BANK_LINE_SIZE_WORDS = 2
)
();
// DRAM Rsponse
wire dram_fill_rsp;
wire [31:0] dram_fill_rsp_addr;
wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_fill_rsp_data;
endinterface
`endif

32
rtl/interfaces/VX_gpu_dcache_req_inter.v
View File

@@ -1,32 +0,0 @@
`include "../VX_cache/VX_cache_config.v"
`ifndef VX_GPU_DCACHE_REQ
`define VX_GPU_DCACHE_REQ
interface VX_gpu_dcache_req_inter
#(
parameter NUMBER_REQUESTS = 32
)
();
// Core Request
wire [NUMBER_REQUESTS-1:0] core_req_valid;
wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr;
wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata;
wire [NUMBER_REQUESTS-1:0][2:0] core_req_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] core_req_mem_write;
wire [4:0] core_req_rd;
wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb;
wire [`NW_M1:0] core_req_warp_num;
wire [31:0] core_req_pc;
// Can't WB
wire core_no_wb_slot;
endinterface
`endif

29
rtl/interfaces/VX_gpu_dcache_res_inter.v
View File

@@ -1,29 +0,0 @@
`include "../VX_cache/VX_cache_config.v"
`ifndef VX_GPU_DCACHE_RES
`define VX_GPU_DCACHE_RES
interface VX_gpu_dcache_res_inter
#(
parameter NUMBER_REQUESTS = 32
)
();
// Cache WB
wire [NUMBER_REQUESTS-1:0] core_wb_valid;
wire [4:0] core_wb_req_rd;
wire [1:0] core_wb_req_wb;
wire [`NW_M1:0] core_wb_warp_num;
wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata;
wire [NUMBER_REQUESTS-1:0][31:0] core_wb_pc;
// Cache Full
wire delay_req;
endinterface
`endif

18
rtl/interfaces/VX_gpu_dcache_snp_req_inter.v
View File

@@ -1,18 +0,0 @@
`include "../VX_cache/VX_cache_config.v"
`ifndef VX_GPU_SNP_REQ
`define VX_GPU_SNP_REQ
interface VX_gpu_dcache_snp_req_inter ();
// Snoop Req
wire snp_req;
wire [31:0] snp_req_addr;
endinterface
`endif

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