project directories reorganization
This commit is contained in:
Blaise Tine
310
hw/rtl/Vortex.v
Normal file
310
hw/rtl/Vortex.v
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`include "VX_define.v"
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`include "VX_cache_config.v"
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module Vortex
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#(
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parameter CORE_ID = 0
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) (
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`ifdef SINGLE_CORE_BENCH
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// Clock
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid,
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output wire[31:0] io_data,
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// DRAM Dcache Req
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output wire dram_req,
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output wire dram_req_write,
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG],
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output wire [31:0] dram_expected_lat,
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input wire dram_req_delay,
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// DRAM Dcache Res
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output wire dram_fill_accept,
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_rsp_addr,
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input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
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// DRAM Icache Req
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output wire I_dram_req,
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output wire I_dram_req_write,
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output wire I_dram_req_read,
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output wire [31:0] I_dram_req_addr,
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output wire [31:0] I_dram_req_size,
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output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
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output wire [31:0] I_dram_expected_lat,
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// DRAM Icache Res
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output wire I_dram_fill_accept,
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input wire I_dram_fill_rsp,
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input wire [31:0] I_dram_fill_rsp_addr,
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input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
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// LLC Snooping
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input wire snp_req,
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input wire [31:0] snp_req_addr,
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output wire snp_req_delay,
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input wire I_snp_req,
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input wire [31:0] I_snp_req_addr,
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output wire I_snp_req_delay,
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output wire out_ebreak
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`else
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid,
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output wire[31:0] io_data,
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// DRAM Dcache Req
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output wire dram_req,
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output wire dram_req_write,
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data,
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output wire [31:0] dram_expected_lat,
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// DRAM Dcache Res
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output wire dram_fill_accept,
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_rsp_addr,
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input wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
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// DRAM Icache Req
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output wire I_dram_req,
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output wire I_dram_req_write,
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output wire I_dram_req_read,
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output wire [31:0] I_dram_req_addr,
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output wire [31:0] I_dram_req_size,
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output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
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output wire [31:0] I_dram_expected_lat,
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// DRAM Icache Res
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output wire I_dram_fill_accept,
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input wire I_dram_fill_rsp,
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input wire [31:0] I_dram_fill_rsp_addr,
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input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
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input wire dram_req_delay,
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input wire snp_req,
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input wire [31:0] snp_req_addr,
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output wire snp_req_delay,
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input wire I_snp_req,
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input wire [31:0] I_snp_req_addr,
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output wire I_snp_req_delay,
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output wire out_ebreak
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`endif
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);
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wire scheduler_empty;
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wire out_ebreak_unqual;
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// assign out_ebreak = out_ebreak_unqual && (scheduler_empty && 1);
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assign out_ebreak = out_ebreak_unqual;
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wire memory_delay;
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wire exec_delay;
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wire gpr_stage_delay;
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wire schedule_delay;
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// Dcache Interface
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VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_rsp();
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VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req();
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VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`DNUMBER_REQUESTS)) VX_dcache_req_qual();
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VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_req();
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VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`DBANK_LINE_SIZE_WORDS)) VX_gpu_dcache_dram_res();
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assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp;
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assign VX_gpu_dcache_dram_res.dram_fill_rsp_addr = dram_fill_rsp_addr;
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assign dram_req = VX_gpu_dcache_dram_req.dram_req;
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assign dram_req_write = VX_gpu_dcache_dram_req.dram_req_write;
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assign dram_req_read = VX_gpu_dcache_dram_req.dram_req_read;
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assign dram_req_addr = VX_gpu_dcache_dram_req.dram_req_addr;
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assign dram_req_size = VX_gpu_dcache_dram_req.dram_req_size;
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assign dram_expected_lat = `DSIMULATED_DRAM_LATENCY_CYCLES;
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assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept;
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assign VX_gpu_dcache_dram_req.dram_req_delay = dram_req_delay;
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genvar wordy;
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generate
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for (wordy = 0; wordy < `DBANK_LINE_SIZE_WORDS; wordy=wordy+1) begin
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assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[wordy] = dram_fill_rsp_data[wordy];
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assign dram_req_data[wordy] = VX_gpu_dcache_dram_req.dram_req_data[wordy];
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end
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endgenerate
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wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write[0] != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000);
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wire[31:0] temp_io_data = VX_dcache_req.core_req_writedata[0];
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assign io_valid = temp_io_valid;
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assign io_data = temp_io_data;
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assign VX_dcache_req_qual.core_req_valid = VX_dcache_req.core_req_valid & {`NT{~io_valid}};
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assign VX_dcache_req_qual.core_req_addr = VX_dcache_req.core_req_addr;
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assign VX_dcache_req_qual.core_req_writedata = VX_dcache_req.core_req_writedata;
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assign VX_dcache_req_qual.core_req_mem_read = VX_dcache_req.core_req_mem_read;
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assign VX_dcache_req_qual.core_req_mem_write = VX_dcache_req.core_req_mem_write;
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assign VX_dcache_req_qual.core_req_rd = VX_dcache_req.core_req_rd;
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assign VX_dcache_req_qual.core_req_wb = VX_dcache_req.core_req_wb;
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assign VX_dcache_req_qual.core_req_warp_num = VX_dcache_req.core_req_warp_num;
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assign VX_dcache_req_qual.core_req_pc = VX_dcache_req.core_req_pc;
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assign VX_dcache_req_qual.core_no_wb_slot = VX_dcache_req.core_no_wb_slot;
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VX_gpu_dcache_res_inter #(.NUMBER_REQUESTS(`INUMBER_REQUESTS)) VX_icache_rsp();
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VX_gpu_dcache_req_inter #(.NUMBER_REQUESTS(`INUMBER_REQUESTS)) VX_icache_req();
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VX_gpu_dcache_dram_req_inter #(.BANK_LINE_SIZE_WORDS(`IBANK_LINE_SIZE_WORDS)) VX_gpu_icache_dram_req();
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VX_gpu_dcache_dram_res_inter #(.BANK_LINE_SIZE_WORDS(`IBANK_LINE_SIZE_WORDS)) VX_gpu_icache_dram_res();
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assign VX_gpu_icache_dram_res.dram_fill_rsp = I_dram_fill_rsp;
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assign VX_gpu_icache_dram_res.dram_fill_rsp_addr = I_dram_fill_rsp_addr;
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assign I_dram_req = VX_gpu_icache_dram_req.dram_req;
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assign I_dram_req_write = VX_gpu_icache_dram_req.dram_req_write;
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assign I_dram_req_read = VX_gpu_icache_dram_req.dram_req_read;
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assign I_dram_req_addr = VX_gpu_icache_dram_req.dram_req_addr;
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assign I_dram_req_size = VX_gpu_icache_dram_req.dram_req_size;
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assign I_dram_expected_lat = `ISIMULATED_DRAM_LATENCY_CYCLES;
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assign I_dram_fill_accept = VX_gpu_icache_dram_req.dram_fill_accept;
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assign VX_gpu_icache_dram_req.dram_req_delay = dram_req_delay;
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genvar iwordy;
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generate
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for (iwordy = 0; iwordy < `IBANK_LINE_SIZE_WORDS; iwordy=iwordy+1) begin
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assign VX_gpu_icache_dram_res.dram_fill_rsp_data[iwordy] = I_dram_fill_rsp_data[iwordy];
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assign I_dram_req_data[iwordy] = VX_gpu_icache_dram_req.dram_req_data[iwordy];
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end
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endgenerate
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/////////////////////////////////////////////////////////////////////////
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// Front-end to Back-end
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VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM
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// Back-end to Front-end
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VX_wb_inter VX_writeback_inter(); // Writeback to GPRs
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VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch
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VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch
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// CSR Buses
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// VX_csr_write_request_inter VX_csr_w_req();
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VX_warp_ctl_inter VX_warp_ctl();
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VX_gpu_snp_req_rsp VX_gpu_icache_snp_req();
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VX_gpu_snp_req_rsp VX_gpu_dcache_snp_req();
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assign VX_gpu_icache_snp_req.snp_req = I_snp_req;
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assign VX_gpu_icache_snp_req.snp_req_addr = I_snp_req_addr;
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assign I_snp_req_delay = VX_gpu_icache_snp_req.snp_delay;
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assign VX_gpu_dcache_snp_req.snp_req = snp_req;
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assign VX_gpu_dcache_snp_req.snp_req_addr = snp_req_addr;
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assign snp_req_delay = VX_gpu_dcache_snp_req.snp_delay;
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VX_front_end vx_front_end(
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.clk (clk),
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.reset (reset),
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.VX_warp_ctl (VX_warp_ctl),
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.VX_bckE_req (VX_bckE_req),
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.schedule_delay (schedule_delay),
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.VX_icache_rsp (VX_icache_rsp),
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.VX_icache_req (VX_icache_req),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp),
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.fetch_ebreak (out_ebreak_unqual)
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);
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VX_scheduler schedule(
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.clk (clk),
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.reset (reset),
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.memory_delay (memory_delay),
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.exec_delay (exec_delay),
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.gpr_stage_delay (gpr_stage_delay),
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.VX_bckE_req (VX_bckE_req),
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.VX_writeback_inter(VX_writeback_inter),
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.schedule_delay (schedule_delay),
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.is_empty (scheduler_empty)
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);
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VX_back_end #(.CORE_ID(CORE_ID)) vx_back_end(
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.clk (clk),
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.reset (reset),
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.schedule_delay (schedule_delay),
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.VX_warp_ctl (VX_warp_ctl),
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.VX_bckE_req (VX_bckE_req),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp),
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.VX_dcache_rsp (VX_dcache_rsp),
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.VX_dcache_req (VX_dcache_req),
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.VX_writeback_inter (VX_writeback_inter),
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.out_mem_delay (memory_delay),
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.out_exec_delay (exec_delay),
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.gpr_stage_delay (gpr_stage_delay)
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);
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VX_dmem_controller VX_dmem_controller(
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.clk (clk),
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.reset (reset),
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// Dram <-> Dcache
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.VX_gpu_dcache_dram_req (VX_gpu_dcache_dram_req),
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.VX_gpu_dcache_dram_res (VX_gpu_dcache_dram_res),
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.VX_gpu_dcache_snp_req (VX_gpu_dcache_snp_req),
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// Dram <-> Icache
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.VX_gpu_icache_dram_req (VX_gpu_icache_dram_req),
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.VX_gpu_icache_dram_res (VX_gpu_icache_dram_res),
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.VX_gpu_icache_snp_req (VX_gpu_icache_snp_req),
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// Core <-> Icache
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.VX_icache_req (VX_icache_req),
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.VX_icache_rsp (VX_icache_rsp),
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// Core <-> Dcache
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.VX_dcache_req (VX_dcache_req_qual),
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.VX_dcache_rsp (VX_dcache_rsp)
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);
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// VX_csr_handler vx_csr_handler(
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// .clk (clk),
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// .in_decode_csr_address(decode_csr_address),
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// .VX_csr_w_req (VX_csr_w_req),
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// .in_wb_valid (VX_writeback_inter.wb_valid[0]),
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// .out_decode_csr_data (csr_decode_csr_data)
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// );
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endmodule // Vortex
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