project directories reorganization
This commit is contained in:
Blaise Tine
36
hw/old_rtl/shared_memory/VX_bank_valids.v
Normal file
36
hw/old_rtl/shared_memory/VX_bank_valids.v
Normal file
@@ -0,0 +1,36 @@
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`include "../VX_define.v"
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// Converts in_valids to bank_valids
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module VX_bank_valids
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#(
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parameter NB = 4,
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parameter BITS_PER_BANK = 3
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)
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(
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input wire[`NT_M1:0] in_valids,
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input wire[`NT_M1:0][31:0] in_addr,
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output reg[NB:0][`NT_M1:0] bank_valids
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);
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integer i, j;
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always@(*) begin
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for(j = 0; j <= NB; j = j+1 ) begin
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for(i = 0; i <= `NT_M1; i = i+1) begin
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if(in_valids[i]) begin
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if(in_addr[i][(2+BITS_PER_BANK-1):2] == j[BITS_PER_BANK-1:0]) begin
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bank_valids[j][i] = 1'b1;
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end
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else begin
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bank_valids[j][i] = 1'b0;
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end
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end
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else begin
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bank_valids[j][i] = 1'b0;
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end
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end
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end
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end
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endmodule
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115
hw/old_rtl/shared_memory/VX_priority_encoder_sm.v
Normal file
115
hw/old_rtl/shared_memory/VX_priority_encoder_sm.v
Normal file
@@ -0,0 +1,115 @@
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`include "../VX_define.v"
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module VX_priority_encoder_sm
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#(
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parameter NB = 4,
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parameter BITS_PER_BANK = 3,
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parameter NUM_REQ = 3
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)
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(
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//INPUTS
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input wire clk,
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input wire reset,
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input wire[`NT_M1:0] in_valid,
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input wire[`NT_M1:0][31:0] in_address,
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input wire[`NT_M1:0][31:0] in_data,
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// OUTPUTS
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// To SM Module
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output reg[NB:0] out_valid,
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output reg[NB:0][31:0] out_address,
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output reg[NB:0][31:0] out_data,
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// To Processor
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output wire[NB:0][`CLOG2(NUM_REQ) - 1:0] req_num,
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output reg stall,
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output wire send_data // Finished all of the requests
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);
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reg[`NT_M1:0] left_requests;
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reg[`NT_M1:0] serviced;
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wire[`NT_M1:0] use_valid;
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wire requests_left = (|left_requests);
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assign use_valid = (requests_left) ? left_requests : in_valid;
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wire[NB:0][`NT_M1:0] bank_valids;
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VX_bank_valids #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_bank_valid(
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.in_valids(use_valid),
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.in_addr(in_address),
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.bank_valids(bank_valids)
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);
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wire[NB:0] more_than_one_valid;
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genvar curr_bank;
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generate
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for (curr_bank = 0; curr_bank <= NB; curr_bank = curr_bank + 1)
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begin
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wire[`CLOG2(`NT):0] num_valids;
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VX_countones #(.N(`NT)) valids_counter (
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.valids(bank_valids[curr_bank]),
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.count (num_valids)
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);
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assign more_than_one_valid[curr_bank] = num_valids > 1;
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// assign more_than_one_valid[curr_bank] = $countones(bank_valids[curr_bank]) > 1;
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end
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endgenerate
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assign stall = (|more_than_one_valid);
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assign send_data = (!stall) && (|in_valid); // change
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wire[NB:0][(`CLOG2(NUM_REQ)) - 1:0] internal_req_num;
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wire[NB:0] internal_out_valid;
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// There's one or less valid per bank
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genvar curr_bank_o;
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for (curr_bank_o = 0; curr_bank_o <= NB; curr_bank_o = curr_bank_o + 1)
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begin
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VX_generic_priority_encoder #(.N(NUM_REQ)) vx_priority_encoder(
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.valids(bank_valids[curr_bank_o]),
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.index(internal_req_num[curr_bank_o]),
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.found(internal_out_valid[curr_bank_o])
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);
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assign out_address[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_address[internal_req_num[curr_bank_o]] : 0;
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assign out_data[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_data[internal_req_num[curr_bank_o]] : 0;
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end
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integer curr_b;
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always @(*) begin
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serviced = 0;
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for (curr_b = 0; curr_b <= NB; curr_b=curr_b+1) begin
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serviced[internal_req_num[curr_b]] = 1;
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end
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end
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assign req_num = internal_req_num;
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assign out_valid = internal_out_valid;
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wire[`NT_M1:0] serviced_qual = in_valid & (serviced);
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wire[`NT_M1:0] new_left_requests = (left_requests == 0) ? (in_valid & ~serviced_qual) : (left_requests & ~ serviced_qual);
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// wire[`NT_M1:0] new_left_requests = left_requests & ~(serviced_qual);
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always @(posedge clk, posedge reset) begin
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if (reset) begin
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left_requests <= 0;
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// serviced = 0;
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end else begin
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if (!stall) left_requests <= 0;
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else left_requests <= new_left_requests;
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end
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end
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endmodule
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178
hw/old_rtl/shared_memory/VX_shared_memory.v
Normal file
178
hw/old_rtl/shared_memory/VX_shared_memory.v
Normal file
@@ -0,0 +1,178 @@
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`include "../VX_define.v"
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module VX_shared_memory
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#(
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parameter SM_SIZE = 4096, // Bytes
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parameter SM_BANKS = 4,
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parameter SM_BYTES_PER_READ = 16,
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parameter SM_WORDS_PER_READ = 4,
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parameter SM_LOG_WORDS_PER_READ = 2,
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parameter SM_HEIGHT = 128, // Bytes
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parameter SM_BANK_OFFSET_START = 2,
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parameter SM_BANK_OFFSET_END = 4,
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parameter SM_BLOCK_OFFSET_START = 5,
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parameter SM_BLOCK_OFFSET_END = 6,
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parameter SM_INDEX_START = 7,
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parameter SM_INDEX_END = 13,
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parameter NUM_REQ = 4,
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parameter BITS_PER_BANK = 3
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)
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(
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//INPUTS
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input wire clk,
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input wire reset,
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input wire[`NT_M1:0] in_valid,
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input wire[`NT_M1:0][31:0] in_address,
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input wire[`NT_M1:0][31:0] in_data,
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input wire[2:0] mem_read,
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input wire[2:0] mem_write,
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//OUTPUTS
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output wire[`NT_M1:0] out_valid,
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output wire[`NT_M1:0][31:0] out_data,
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output wire stall
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);
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//reg[NB:0][31:0] temp_address;
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//reg[NB:0][31:0] temp_in_data;
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//reg[NB:0] temp_in_valid;
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reg[SM_BANKS - 1:0][31:0] temp_address;
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reg[SM_BANKS - 1:0][31:0] temp_in_data;
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reg[SM_BANKS - 1:0] temp_in_valid;
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reg[`NT_M1:0] temp_out_valid;
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reg[`NT_M1:0][31:0] temp_out_data;
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//reg [NB:0][6:0] block_addr;
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//reg [NB:0][3:0][31:0] block_wdata;
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//reg [NB:0][3:0][31:0] block_rdata;
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//reg [NB:0][1:0] block_we;
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reg [SM_BANKS - 1:0][$clog2(SM_HEIGHT) - 1:0] block_addr;
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reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_wdata;
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reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_rdata;
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reg [SM_BANKS - 1:0][SM_LOG_WORDS_PER_READ-1:0] block_we;
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wire send_data;
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//reg[NB:0][1:0] req_num;
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reg[SM_BANKS - 1:0][`CLOG2(NUM_REQ) - 1:0] req_num; // not positive about this
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wire [`NT_M1:0] orig_in_valid;
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genvar f;
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generate
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for(f = 0; f < `NT; f = f+1) begin
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assign orig_in_valid[f] = in_valid[f];
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end
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assign out_valid = send_data ? temp_out_valid : 0;
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assign out_data = send_data ? temp_out_data : 0;
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endgenerate
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//VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm(
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VX_priority_encoder_sm #(.NB(SM_BANKS - 1), .BITS_PER_BANK(BITS_PER_BANK), .NUM_REQ(NUM_REQ)) vx_priority_encoder_sm(
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.clk(clk),
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.reset(reset),
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.in_valid(orig_in_valid),
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.in_address(in_address),
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.in_data(in_data),
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.out_valid(temp_in_valid),
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.out_address(temp_address),
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.out_data(temp_in_data),
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.req_num(req_num),
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.stall(stall),
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.send_data(send_data)
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);
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genvar j;
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integer i;
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generate
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//for(j=0; j<= NB; j=j+1) begin : sm_mem_block
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for(j=0; j<= SM_BANKS - 1; j=j+1) begin
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wire shm_write = (mem_write != `NO_MEM_WRITE) && temp_in_valid[j];
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VX_shared_memory_block#
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(
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.SMB_HEIGHT(SM_HEIGHT),
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.SMB_WORDS_PER_READ(SM_WORDS_PER_READ),
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.SMB_LOG_WORDS_PER_READ(SM_LOG_WORDS_PER_READ)
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) vx_shared_memory_block
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(
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.clk (clk),
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.reset (reset),
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.addr (block_addr[j]),
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.wdata (block_wdata[j]),
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.we (block_we[j]),
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.shm_write(shm_write),
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.data_out (block_rdata[j])
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);
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end
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always @(*) begin
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block_addr = 0;
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block_we = 0;
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block_wdata = 0;
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//for(i = 0; i <= NB; i = i+1) begin
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for(i = 0; i <= SM_BANKS - 1; i = i+1) begin
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if(temp_in_valid[i] == 1'b1) begin
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//1. Check if the request is actually to the shared memory
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if((temp_address[i][31:24]) == 8'hFF) begin
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// STORES
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if(mem_write != `NO_MEM_WRITE) begin
|
||||
if(mem_write == `SB_MEM_WRITE) begin
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//TODO
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||||
end
|
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else if(mem_write == `SH_MEM_WRITE) begin
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//TODO
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||||
end
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else if(mem_write == `SW_MEM_WRITE) begin
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//block_addr[i] = temp_address[i][13:7];
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//block_we[i] = temp_address[i][6:5];
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//block_wdata[i][temp_address[i][6:5]] = temp_in_data[i];
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block_addr[i] = temp_address[i][SM_INDEX_END:SM_INDEX_START];
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block_we[i] = temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START];
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block_wdata[i][temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]] = temp_in_data[i];
|
||||
end
|
||||
end
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//LOADS
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else if(mem_read != `NO_MEM_READ) begin
|
||||
if(mem_read == `LB_MEM_READ) begin
|
||||
//TODO
|
||||
end
|
||||
else if (mem_read == `LH_MEM_READ)
|
||||
begin
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||||
//TODO
|
||||
end
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||||
else if (mem_read == `LW_MEM_READ)
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begin
|
||||
//block_addr[i] = temp_address[i][13:7];
|
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//temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][6:5]];
|
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//temp_out_valid[req_num[i]] = 1'b1;
|
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block_addr[i] = temp_address[i][SM_INDEX_END:SM_INDEX_START];
|
||||
temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]];
|
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temp_out_valid[req_num[i]] = 1'b1;
|
||||
end
|
||||
else if (mem_read == `LBU_MEM_READ)
|
||||
begin
|
||||
//TODO
|
||||
end
|
||||
else if (mem_read == `LHU_MEM_READ)
|
||||
begin
|
||||
//TODO
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
|
||||
endmodule
|
||||
115
hw/old_rtl/shared_memory/VX_shared_memory_block.v
Normal file
115
hw/old_rtl/shared_memory/VX_shared_memory_block.v
Normal file
@@ -0,0 +1,115 @@
|
||||
module VX_shared_memory_block
|
||||
#(
|
||||
parameter SMB_SIZE = 4096, // Bytes
|
||||
parameter SMB_BYTES_PER_READ = 16,
|
||||
parameter SMB_WORDS_PER_READ = 4,
|
||||
parameter SMB_LOG_WORDS_PER_READ = 2,
|
||||
parameter SMB_HEIGHT = 128, // Bytes
|
||||
parameter BITS_PER_BANK = 3
|
||||
)
|
||||
(
|
||||
input wire clk, // Clock
|
||||
input wire reset,
|
||||
//input wire[6:0] addr,
|
||||
//input wire[3:0][31:0] wdata,
|
||||
//input wire[1:0] we,
|
||||
//input wire shm_write,
|
||||
|
||||
//output wire[3:0][31:0] data_out
|
||||
input wire[$clog2(SMB_HEIGHT) - 1:0] addr,
|
||||
input wire[SMB_WORDS_PER_READ-1:0][31:0] wdata,
|
||||
input wire[SMB_LOG_WORDS_PER_READ-1:0] we,
|
||||
input wire shm_write,
|
||||
|
||||
output wire[SMB_WORDS_PER_READ-1:0][31:0] data_out
|
||||
|
||||
);
|
||||
|
||||
|
||||
`ifndef SYN
|
||||
|
||||
//reg[3:0][31:0] shared_memory[127:0];
|
||||
reg[SMB_WORDS_PER_READ-1:0][31:0] shared_memory[SMB_HEIGHT-1:0];
|
||||
|
||||
//wire need_to_write = (|we);
|
||||
integer curr_ind;
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
//for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1)
|
||||
for (curr_ind = 0; curr_ind < SMB_HEIGHT; curr_ind = curr_ind + 1)
|
||||
begin
|
||||
shared_memory[curr_ind] = 0;
|
||||
end
|
||||
end else if(shm_write) begin
|
||||
shared_memory[addr][we][31:0] = wdata[we][31:0]; // - Ethan's addition
|
||||
//if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
|
||||
//if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
|
||||
//if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
|
||||
//if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign data_out = shm_write ? 0 : shared_memory[addr];
|
||||
|
||||
`else
|
||||
|
||||
wire cena = 0;
|
||||
wire cenb = !shm_write;
|
||||
|
||||
wire[3:0][31:0] write_bit_mask;
|
||||
|
||||
//assign write_bit_mask[0] = (we == 2'b00) ? {32{1'b1}} : {32{1'b0}};
|
||||
//assign write_bit_mask[1] = (we == 2'b01) ? {32{1'b1}} : {32{1'b0}};
|
||||
//assign write_bit_mask[2] = (we == 2'b10) ? {32{1'b1}} : {32{1'b0}};
|
||||
//assign write_bit_mask[3] = (we == 2'b11) ? {32{1'b1}} : {32{1'b0}};
|
||||
genvar curr_word;
|
||||
for (curr_word = 0; curr_word < SMB_WORDS_PER_READ; curr_word = curr_word + 1)
|
||||
begin
|
||||
assign write_bit_mask[curr_word] = (we == curr_word) ? 1 : {32{1'b0}};
|
||||
end
|
||||
|
||||
// Using ASIC MEM
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
rf2_128x128_wm1 first_ram (
|
||||
.CENYA(),
|
||||
.AYA(),
|
||||
.CENYB(),
|
||||
.WENYB(),
|
||||
.AYB(),
|
||||
.QA(data_out),
|
||||
.SOA(),
|
||||
.SOB(),
|
||||
.CLKA(clk),
|
||||
.CENA(cena),
|
||||
.AA(addr),
|
||||
.CLKB(clk),
|
||||
.CENB(cenb),
|
||||
.WENB(write_bit_mask),
|
||||
.AB(addr),
|
||||
.DB(wdata),
|
||||
.EMAA(3'b011),
|
||||
.EMASA(1'b0),
|
||||
.EMAB(3'b011),
|
||||
.TENA(1'b1),
|
||||
.TCENA(1'b0),
|
||||
.TAA(7'b0),
|
||||
.TENB(1'b1),
|
||||
.TCENB(1'b0),
|
||||
.TWENB(128'b0),
|
||||
.TAB(7'b0),
|
||||
.TDB(128'b0),
|
||||
.RET1N(1'b1),
|
||||
.SIA(2'b0),
|
||||
.SEA(1'b0),
|
||||
.DFTRAMBYP(1'b0),
|
||||
.SIB(2'b0),
|
||||
.SEB(1'b0),
|
||||
.COLLDISN(1'b1)
|
||||
);
|
||||
/* verilator lint_on PINCONNECTEMPTY */
|
||||
|
||||
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user