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This commit is contained in:
Blaise Tine
2020-04-14 06:35:20 -04:00
parent 1de06fd9c0
commit fc155e1223
1056 changed files with 8120 additions and 8120 deletions
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124
hw/modelsim/Makefile Normal file
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ALL:sim
#TOOL INPUT
SRC = \
vortex_dpi.cpp \
vortex_tb.v \
../VX_define.v \
../VX_define_synth.v \
../interfaces/VX_branch_response_inter.v \
../interfaces/VX_csr_req_inter.v \
../interfaces/VX_csr_wb_inter.v \
../interfaces/VX_dcache_request_inter.v \
../interfaces/VX_dcache_response_inter.v \
../interfaces/VX_dram_req_rsp_inter.v \
../interfaces/VX_exec_unit_req_inter.v \
../interfaces/VX_frE_to_bckE_req_inter.v \
../interfaces/VX_gpr_clone_inter.v \
../interfaces/VX_gpr_data_inter.v \
../interfaces/VX_gpr_jal_inter.v \
../interfaces/VX_gpr_read_inter.v \
../interfaces/VX_gpr_wspawn_inter.v \
../interfaces/VX_gpu_inst_req_inter.v \
../interfaces/VX_icache_request_inter.v \
../interfaces/VX_icache_response_inter.v \
../interfaces/VX_inst_exec_wb_inter.v \
../interfaces/VX_inst_mem_wb_inter.v \
../interfaces/VX_inst_meta_inter.v \
../interfaces/VX_jal_response_inter.v \
../interfaces/VX_join_inter.v \
../interfaces/VX_lsu_req_inter.v \
../interfaces/VX_mem_req_inter.v \
../interfaces/VX_mw_wb_inter.v \
../interfaces/VX_warp_ctl_inter.v \
../interfaces/VX_wb_inter.v \
../interfaces/VX_wstall_inter.v \
../VX_alu.v \
../VX_back_end.v \
../VX_csr_handler.v \
../VX_csr_wrapper.v \
../VX_decode.v \
../VX_dmem_controller.v \
../VX_execute_unit.v \
../VX_fetch.v \
../VX_front_end.v \
../VX_generic_priority_encoder.v \
../VX_generic_register.v \
../VX_generic_stack.v \
../VX_gpgpu_inst.v \
../VX_gpr.v \
../VX_gpr_stage.v \
../VX_gpr_wrapper.v \
../VX_inst_multiplex.v \
../VX_lsu.v \
../VX_lsu_addr_gen.v \
../VX_priority_encoder.v \
../VX_priority_encoder_w_mask.v \
../VX_scheduler.v \
../VX_warp.v \
../VX_countones.v \
../VX_warp_scheduler.v \
../VX_writeback.v \
../Vortex.v \
../byte_enabled_simple_dual_port_ram.v \
../cache/VX_Cache_Bank.v \
../cache/VX_cache_bank_valid.v \
../cache/VX_cache_data.v \
../cache/VX_d_cache.v \
../cache/VX_generic_pe.v \
../cache/cache_set.v \
../cache/VX_cache_data_per_index.v \
../pipe_regs/VX_d_e_reg.v \
../pipe_regs/VX_f_d_reg.v \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v \
../../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \
../../models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v \
../../models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.v
# ../../models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
# vortex_dpi.h
CMD= \
-do "VoptFlow = 0; \
vcd file vortex.vcd; \
vcd add -r /vortex_tb/*; \
vcd add -r /vortex/*; \
run -all; \
quit -f"
OPT=-sv -sv12compat
LIB = vortex_lib
# LOG=-logfile vortex_tb.log
LOG=
# setup: source cshrc.modelsim
# vlib
lib:
vlib vortex_lib
comp:
vlog $(OPT) -work $(LIB) $(SRC)
# vlog -O0 -dpiheader vortex_dpi.h $(OPT) -work $(LIB) $(SRC)
sim: comp
# vsim vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log
vsim -novopt vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log

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setenv PATH "${PATH}:/tools/mentor/modelsim/ms106a/modeltech/bin"
setenv MTI_VCO_MODE 1
if (${?LM_LICENSE_FILE}) then
setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu:${LM_LICENSE_FILE}"
else
setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu"
endif
setenv MGLS_LICENSE_FILE 1717@ece-linlic.ece.gatech.edu

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hw/modelsim/vortex_dpi.cpp Normal file
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// #include <iostream>
// #include "VX_define.h"
#include <../simulate/ram.h>
#include <stdio.h>
#include <math.h>
#include "svdpi.h"
#include "../simulate/VX_define.h"
// #include "vortex_dpi.h"
extern "C" {
void load_file (char * filename);
void ibus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void io_handler (bool clk, bool io_valid, unsigned io_data);
void gracefulExit(int);
}
RAM ram;
bool refill;
unsigned refill_addr;
bool i_refill;
unsigned i_refill_addr;
unsigned num_cycles;
unsigned getIndex(int, int, int);
unsigned calculate_bits_per_bank_num(int);
unsigned getIndex(int r, int c, int numCols)
{
return (r * numCols) + c;
}
unsigned calculate_bits_per_bank_num(int num)
{
int shifted_num = 0;
for(int i = 0; i < num; i++){
shifted_num = (shifted_num << 1)| 1 ;
}
return shifted_num;
}
void load_file(char * filename)
{
num_cycles = 0;
// printf("\n\n\n\n**********************\n");
// printf("Inside load_file\n");
fprintf(stderr, "\n\n\n\n**********************\n");
loadHexImpl(filename, &ram);
// printf("Filename: %s\n", filename);
refill = false;
i_refill = false;
}
void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready)
{
// Default values
{
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
(*i_m_ready) = false;
for (int i = 0; i < cache_banks; i++)
{
for (int j = 0; j < num_words_per_block; j++)
{
unsigned index = getIndex(i,j, num_words_per_block);
real_i_m_readdata[index].aval = 0x506070;
// svGetArrElemPtr2(i_m_readdata, i, j);
// svPutLogicArrElem2VecVal(i_m_readdata, i, j);
// i_m_readdata[getIndex(i,j, num_words_per_block)] = 0;
}
}
}
if (clk)
{
// Do nothing on positive edge
}
else
{
if (i_refill)
{
// svGetArrElemPtr2((*i_m_readdata), 0,0);
// fprintf(stderr, "--------------------------------\n");
i_refill = false;
*i_m_ready = true;
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = i_refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
unsigned value;
ram.getWord(new_addr, &value);
fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value);
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
// fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value);
real_i_m_readdata[index].aval = value;
}
}
else
{
if (o_m_valid)
{
s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata;
if (o_m_read_or_write)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
// unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
unsigned new_value = real_o_m_writedata[index].aval;
// new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num);
// new_value = getElem(o_m_writedata, index);
// unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)];
ram.writeWord( new_addr, &new_value);
fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value);
}
}
// Respond next cycle
i_refill = true;
i_refill_addr = o_m_read_addr;
}
}
}
}
void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready)
{
// Default values
{
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
(*i_m_ready) = false;
for (int i = 0; i < cache_banks; i++)
{
for (int j = 0; j < num_words_per_block; j++)
{
unsigned index = getIndex(i,j, num_words_per_block);
real_i_m_readdata[index].aval = 0x506070;
// svGetArrElemPtr2(i_m_readdata, i, j);
// svPutLogicArrElem2VecVal(i_m_readdata, i, j);
// i_m_readdata[getIndex(i,j, num_words_per_block)] = 0;
}
}
}
if (clk)
{
// Do nothing on positive edge
}
else
{
if (refill)
{
// svGetArrElemPtr2((*i_m_readdata), 0,0);
// fprintf(stderr, "--------------------------------\n");
refill = false;
*i_m_ready = true;
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
unsigned value;
ram.getWord(new_addr, &value);
fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value);
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
// fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value);
real_i_m_readdata[index].aval = value;
}
}
else
{
if (o_m_valid)
{
s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata;
if (o_m_read_or_write)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
// unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
unsigned new_value = real_o_m_writedata[index].aval;
// new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num);
// new_value = getElem(o_m_writedata, index);
// unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)];
ram.writeWord( new_addr, &new_value);
fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value);
}
}
// Respond next cycle
refill = true;
refill_addr = o_m_read_addr;
}
}
}
}
void io_handler(bool clk, bool io_valid, unsigned io_data)
{
// printf("Inside io_handler\n");
if (clk)
{
// Do nothing
}
else
{
if (io_valid)
{
uint32_t data_write = (uint32_t) (io_data);
fprintf(stderr, "%c", (char) data_write);
fflush(stderr);
}
}
}
void gracefulExit(int cycles)
{
fprintf(stderr, "*********************\n\n");
fprintf(stderr, "DPI Cycle Num: %d\tVerilog Cycle Num: %d\n", num_cycles, cycles);
}

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extern "C" {
void load_file (char * filename);
void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void io_handler (bool clk, bool io_valid, unsigned io_data);
void gracefulExit();
}

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`include "../VX_define.v"
//`define NUMBER_BANKS 8
//`define NUM_WORDS_PER_BLOCK 4
`define ARM_UD_MODEL
`timescale 1ns/1ps
import "DPI-C" load_file = function void load_file(input string filename);
/*
import "DPI-C" ibus_driver = function void ibus_driver(input logic clk, input int pc_addr,
output int instruction);
*/
import "DPI-C" ibus_driver = function void ibus_driver( input logic clk,
input int o_m_read_addr,
input int o_m_evict_addr,
input logic o_m_valid,
input reg[31:0] o_m_writedata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0],
input logic o_m_read_or_write,
input int cache_banks,
input int words_per_block,
// Rsp
output reg[31:0] i_m_readdata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0],
output logic i_m_ready);
import "DPI-C" dbus_driver = function void dbus_driver( input logic clk,
input int o_m_read_addr,
input int o_m_evict_addr,
input logic o_m_valid,
input reg[31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
input logic o_m_read_or_write,
input int cache_banks,
input int words_per_block,
// Rsp
output reg[31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
output logic i_m_ready);
import "DPI-C" io_handler = function void io_handler(input logic clk, input logic io_valid, input int io_data);
import "DPI-C" gracefulExit = function void gracefulExit(input int cycle_num);
module vortex_tb (
);
int cycle_num;
reg clk;
reg reset;
reg[31:0] icache_response_instruction;
reg[31:0] icache_request_pc_address;
// IO
reg io_valid;
reg[31:0] io_data;
// Req
reg [31:0] o_m_read_addr_d;
reg [31:0] o_m_evict_addr_d;
reg o_m_valid_d;
reg [31:0] o_m_writedata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0];
reg o_m_read_or_write_d;
// Rsp
reg [31:0] i_m_readdata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0];
reg i_m_ready_d;
// Req
reg [31:0] o_m_read_addr_i;
reg [31:0] o_m_evict_addr_i;
reg o_m_valid_i;
reg [31:0] o_m_writedata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0];
reg o_m_read_or_write_i;
// Rsp
reg [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0];
reg i_m_ready_i;
reg out_ebreak;
reg[31:0] hi;
integer temp;
initial begin
// $fdumpfile("vortex1.vcd");
load_file("../../runtime/mains/simple/vx_simple_main.hex");
// load_file("../../emulator/riscv_tests/rv32ui-p-add.hex");
//load_file("../../kernel/vortex_test.hex");
$dumpvars(0, vortex_tb);
reset = 1;
clk = 0;
#5 reset = 1;
clk = 1;
cycle_num = 0;
end
Vortex vortex(
.clk (clk),
.reset (reset),
.icache_response_instruction (icache_response_instruction),
.icache_request_pc_address (icache_request_pc_address),
.io_valid (io_valid),
.io_data (io_data),
.o_m_read_addr_d (o_m_read_addr_d),
.o_m_evict_addr_d (o_m_evict_addr_d),
.o_m_valid_d (o_m_valid_d),
.o_m_writedata_d (o_m_writedata_d),
.o_m_read_or_write_d (o_m_read_or_write_d),
.i_m_readdata_d (i_m_readdata_d),
.i_m_ready_d (i_m_ready_d),
.o_m_read_addr_i (o_m_read_addr_i),
.o_m_evict_addr_i (o_m_evict_addr_i),
.o_m_valid_i (o_m_valid_i),
.o_m_writedata_i (o_m_writedata_i),
.o_m_read_or_write_i (o_m_read_or_write_i),
.i_m_readdata_i (i_m_readdata_i),
.i_m_ready_i (i_m_ready_i),
.out_ebreak (out_ebreak)
);
always @(negedge clk) begin
ibus_driver(clk, o_m_read_addr_i, o_m_evict_addr_i, o_m_valid_i, o_m_writedata_i, o_m_read_or_write_i, `ICACHE_BANKS, `ICACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_i, i_m_ready_i);
dbus_driver(clk, o_m_read_addr_d, o_m_evict_addr_d, o_m_valid_d, o_m_writedata_d, o_m_read_or_write_d, `DCACHE_BANKS, `DCACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_d, i_m_ready_d);
io_handler (clk, io_valid, io_data);
end
always @(posedge clk) begin
if (out_ebreak) begin
gracefulExit(cycle_num);
#40 $finish;
end
end
always @(posedge clk) begin
cycle_num = cycle_num + 1;
end
always @(clk, posedge reset) begin
if (reset) begin
reset = 0;
clk = 0;
end
#5 clk <= ~clk;
end
endmodule

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m255
K4
z0
cModel Technology