bilinear fixes + refactoring

2021-03-31 23:30:36 -04:00
parent 99ca04ce8c
commit fa2d84831e
7 changed files with 106 additions and 223 deletions
--- a/hw/rtl/tex_unit/VX_tex_unit.v
+++ b/hw/rtl/tex_unit/VX_tex_unit.v
@@ -190,7 +190,7 @@ module VX_tex_unit #(
    wire [`NR_BITS-1:0]         rsp_rd;   
    wire                        rsp_wb;
    
-    assign {rsp_format, rsp_u, rsp_v, rsp_rd, rsp_wb} = mem_rsp_info;
+    assign {rsp_u, rsp_v, rsp_format, rsp_rd, rsp_wb} = mem_rsp_info;

    VX_tex_sampler #(
        .CORE_ID (CORE_ID)