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fixed bank_core_req_arb critical path.

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This commit is contained in:
Blaise Tine
2020-12-01 08:43:59 -08:00
parent f68af3bb84
commit f9d98c5a2b
6 changed files with 65 additions and 48 deletions
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1
hw/opae/sources_1c.txt
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@@ -23,6 +23,7 @@ vortex_afu.json
QI:vortex_afu.qsf QI:vortex_afu.qsf
ccip_interface_reg.sv ccip_interface_reg.sv
ccip_std_afu.sv ccip_std_afu.sv
VX_avs_wrapper.sv
vortex_afu.sv vortex_afu.sv
C:sources.txt C:sources.txt

1
hw/opae/sources_2c.txt
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@@ -8,6 +8,7 @@ vortex_afu.json
QI:vortex_afu.qsf QI:vortex_afu.qsf
ccip_interface_reg.sv ccip_interface_reg.sv
ccip_std_afu.sv ccip_std_afu.sv
VX_avs_wrapper.sv
vortex_afu.sv vortex_afu.sv
C:sources.txt C:sources.txt

1
hw/opae/sources_4c.txt
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@@ -8,6 +8,7 @@ vortex_afu.json
QI:vortex_afu.qsf QI:vortex_afu.qsf
ccip_interface_reg.sv ccip_interface_reg.sv
ccip_std_afu.sv ccip_std_afu.sv
VX_avs_wrapper.sv
vortex_afu.sv vortex_afu.sv
C:sources.txt C:sources.txt

17
hw/rtl/VX_csr_arb.v
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@@ -1,22 +1,23 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_csr_arb ( module VX_csr_arb (
// inputs // bus select
input wire select_io_req,
input wire select_io_rsp,
// input requets
VX_csr_req_if csr_core_req_if, VX_csr_req_if csr_core_req_if,
VX_csr_io_req_if csr_io_req_if, VX_csr_io_req_if csr_io_req_if,
// output // output request
VX_csr_req_if csr_req_if, VX_csr_req_if csr_req_if,
// input // input response
VX_commit_if csr_rsp_if, VX_commit_if csr_rsp_if,
// outputs // outputs responses
VX_commit_if csr_commit_if, VX_commit_if csr_commit_if,
VX_csr_io_rsp_if csr_io_rsp_if, VX_csr_io_rsp_if csr_io_rsp_if
input wire select_io_req,
input wire select_io_rsp
); );
// requests // requests
assign csr_req_if.valid = (~select_io_req) ? csr_core_req_if.valid : csr_io_req_if.valid; assign csr_req_if.valid = (~select_io_req) ? csr_core_req_if.valid : csr_io_req_if.valid;

8
hw/rtl/VX_csr_unit.v
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@@ -26,16 +26,16 @@ module VX_csr_unit #(
wire select_io_rsp; wire select_io_rsp;
VX_csr_arb csr_arb ( VX_csr_arb csr_arb (
.select_io_req (select_io_req),
.select_io_rsp (select_io_rsp),
.csr_core_req_if (csr_req_if), .csr_core_req_if (csr_req_if),
.csr_io_req_if (csr_io_req_if), .csr_io_req_if (csr_io_req_if),
.csr_req_if (csr_pipe_req_if), .csr_req_if (csr_pipe_req_if),
.csr_rsp_if (csr_pipe_rsp_if), .csr_rsp_if (csr_pipe_rsp_if),
.csr_io_rsp_if (csr_io_rsp_if), .csr_io_rsp_if (csr_io_rsp_if),
.csr_commit_if (csr_commit_if), .csr_commit_if (csr_commit_if)
.select_io_req (select_io_req),
.select_io_rsp (select_io_rsp)
); );
wire csr_we_s1; wire csr_we_s1;

85
hw/rtl/cache/VX_bank_core_req_arb.v vendored
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@@ -72,33 +72,44 @@ module VX_bank_core_req_arb #(
if (NUM_REQUESTS > 1) begin if (NUM_REQUESTS > 1) begin
reg [CORE_TAG_WIDTH-1:0] sel_tag; reg [`REQS_BITS-1:0] sel_idx, sel_idx_r;
reg [`REQS_BITS-1:0] sel_tid; reg [CORE_TAG_WIDTH-1:0] sel_tag, sel_tag_r;
reg [`WORD_ADDR_WIDTH-1:0] sel_addr; reg [`WORD_ADDR_WIDTH-1:0] sel_addr, sel_addr_r;
reg sel_rw; reg sel_rw, sel_rw_r;
reg [WORD_SIZE-1:0] sel_byteen; reg [WORD_SIZE-1:0] sel_byteen, sel_byteen_r;
reg [`WORD_WIDTH-1:0] sel_writedata; reg [`WORD_WIDTH-1:0] sel_writedata, sel_writedata_r;
reg [$clog2(NUM_REQUESTS+1)-1:0] q_valids_cnt_r; reg [$clog2(NUM_REQUESTS+1)-1:0] q_valids_cnt_r;
wire [$clog2(NUM_REQUESTS+1)-1:0] q_valids_cnt; wire [$clog2(NUM_REQUESTS+1)-1:0] q_valids_cnt;
reg [NUM_REQUESTS-1:0] pop_mask;
reg fast_track; reg [NUM_REQUESTS-1:0] pop_mask;
reg fast_track;
assign q_push = push; assign q_push = push;
assign q_pop = pop && (q_valids_cnt_r == 1 || q_valids_cnt_r == 2) && !fast_track; assign q_pop = pop && (q_valids_cnt_r == 1 || q_valids_cnt_r == 2) && !fast_track;
wire [`REQS_BITS-1:0] sel_idx; wire [NUM_REQUESTS-1:0] requests = q_valids & ~pop_mask;
VX_fixed_arbiter #( always @(*) begin
.N(NUM_REQUESTS) sel_idx = 0;
) sel_arb ( sel_tag = 'x;
.clk (clk), sel_addr = 'x;
.reset (reset), sel_rw = 'x;
.requests (q_valids & ~pop_mask), sel_byteen = 'x;
`UNUSED_PIN (grant_valid), sel_writedata = 'x;
.grant_index (sel_idx),
`UNUSED_PIN (grant_onehot) for (integer i = 0; i < NUM_REQUESTS; i++) begin
); if (requests[i]) begin
sel_idx = `REQS_BITS'(i);
sel_tag = q_tag[i];
sel_addr = q_addr[i];
sel_rw = q_rw[i];
sel_byteen = q_byteen[i];
sel_writedata = q_writedata[i];
break;
end
end
end
VX_countones #( VX_countones #(
.N(NUM_REQUESTS) .N(NUM_REQUESTS)
@@ -130,35 +141,37 @@ module VX_bank_core_req_arb #(
end end
if ((0 == q_valids_cnt_r) || pop) begin if ((0 == q_valids_cnt_r) || pop) begin
sel_tid <= sel_idx; sel_idx_r <= sel_idx;
sel_byteen <= q_byteen[sel_idx]; sel_byteen_r <= sel_byteen;
sel_addr <= q_addr[sel_idx]; sel_addr_r <= sel_addr;
sel_writedata <= q_writedata[sel_idx]; sel_writedata_r <= sel_writedata;
end end
end end
if (CORE_TAG_ID_BITS != 0) begin if (CORE_TAG_ID_BITS != 0) begin
`UNUSED_VAR (sel_tag)
`UNUSED_VAR (sel_rw)
always @(posedge clk) begin always @(posedge clk) begin
if ((0 == q_valids_cnt_r) || pop) begin if ((0 == q_valids_cnt_r) || pop) begin
sel_tag <= q_tag; sel_tag_r <= q_tag;
sel_rw <= q_rw; sel_rw_r <= q_rw;
end end
end end
end else begin end else begin
always @(posedge clk) begin always @(posedge clk) begin
if ((0 == q_valids_cnt_r) || pop) begin if ((0 == q_valids_cnt_r) || pop) begin
sel_tag <= q_tag[sel_idx]; sel_tag_r <= sel_tag;
sel_rw <= q_rw[sel_idx]; sel_rw_r <= sel_rw;
end end
end end
end end
assign tag_out = sel_tag; assign tag_out = sel_tag_r;
assign addr_out = sel_addr; assign addr_out = sel_addr_r;
assign rw_out = sel_rw; assign rw_out = sel_rw_r;
assign byteen_out = sel_byteen; assign byteen_out = sel_byteen_r;
assign writedata_out = sel_writedata; assign writedata_out = sel_writedata_r;
assign tid_out = sel_tid; assign tid_out = sel_idx_r;
assign empty = (0 == q_valids_cnt_r); assign empty = (0 == q_valids_cnt_r);
assign full = q_full; assign full = q_full;