mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL

hw/simulate/Makefile

@@ -42,7 +42,7 @@ gen-s:
 	verilator $(VF) -DNDEBUG  $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG $(SINGLECORE)'
 
 gen-sd:
-	verilator $(VF) $(SINGLECORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(SINGLECORE)' --trace $(DBG)
+	verilator $(VF) -O0 $(SINGLECORE) -CFLAGS '$(CF) -O0 -g $(DBG) $(SINGLECORE)' --trace $(DBG)
 
 gen-st:
 	verilator $(VF) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(SINGLECORE)' --threads $(THREADS)
@@ -51,7 +51,7 @@ gen-m:
 	verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'
 	
 gen-md:
-	verilator $(VF) $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG)
+	verilator $(VF) $(MULTICORE) -CFLAGS '$(CF) -O0 -g $(DBG) $(MULTICORE)' --trace $(DBG)
 
 gen-mt:
 	verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS)
@@ -60,7 +60,7 @@ build-s: gen-s
 	(cd obj_dir && make -j -f VVortex.mk)
 
 build-sd: gen-sd
-	(cd obj_dir && make -j -f VVortex.mk)
+	(cd obj_dir && OPT_FAST="-O0 -g" make -j -f VVortex.mk)
 
 build-st: gen-st
 	(cd obj_dir && make -j -f VVortex.mk)
@@ -69,7 +69,7 @@ build-m: gen-m
 	(cd obj_dir && make -j -f VVortex.mk)
 
 build-md: gen-md
-	(cd obj_dir && make -j -f VVortex.mk)
+	(cd obj_dir && OPT_FAST="-O0 -g" make -j -f VVortex.mk)
 
 build-mt: gen-mt
 	(cd obj_dir && make -j -f VVortex.mk)
@@ -79,7 +79,7 @@ run-s: build-s
 	(cd obj_dir && ./VVortex)
 
 run-sd: build-sd
-	(cd obj_dir && ./VVortex)
+	(cd obj_dir && valgrind ./VVortex)
 
 run-st: build-st
 	(cd obj_dir && ./VVortex)

hw/simulate/simulator.cpp

@@ -8,6 +8,9 @@
 #define DRAM_RQ_SIZE 16
 #define DRAM_STALLS_MODULO 16
 
+#define VL_WDATA_GETW(lwp, i, n, w) \
+  VL_SEL_IWII(0, n * w, 0, 0, lwp, i * w, w)
+
 uint64_t timestamp = 0;
 
 double sc_time_stamp() { 
@@ -35,9 +38,18 @@ Simulator::Simulator() {
   vortex_->trace(trace_, 99);
   trace_->open("trace.vcd");
 #endif  
+
+  // reset the device
+  this->reset();
 }
 
 Simulator::~Simulator() {
+  for (auto& buf : print_bufs_) {
+    auto str = buf.second.str();
+    if (str.size()) {
+      std::cout << "#" << buf.first << ": " << buf.second.str() << std::endl;
+    }
+  }
 #ifdef VCD_OUTPUT
   trace_->close();
 #endif
@@ -158,12 +170,20 @@ void Simulator::eval_dram_bus() {
 }
 
 void Simulator::eval_io_bus() {
-  if (vortex_->io_req_valid
-   && vortex_->io_req_rw 
-   && ((vortex_->io_req_addr << 2) == IO_BUS_ADDR_COUT)) {
-    uint32_t data_write = (uint32_t)vortex_->io_req_data;
-    char c = (char)data_write;
-    std::cout << c;      
+  for (int i = 0; i < NUM_THREADS; ++i) {
+    if (((vortex_->io_req_valid >> i) & 0x1) 
+     && ((VL_WDATA_GETW(vortex_->io_req_addr, i, NUM_THREADS, 30) << 2) == IO_BUS_ADDR_COUT)) {
+      assert(vortex_->io_req_rw);
+      int data = vortex_->io_req_data[i];
+      int tid = data >> 16;
+      char c = data & 0xff;
+      auto& ss_buf = print_bufs_[tid];
+      ss_buf << c;
+      if (c == '\n') {
+        std::cout << std::dec << "#" << tid << ": " << ss_buf.str() << std::flush;
+        ss_buf.str("");
+      }         
+    }
   }
   vortex_->io_req_ready = 1;
   vortex_->io_rsp_valid = 0;
@@ -229,9 +249,15 @@ void Simulator::wait(uint32_t cycles) {
 }
 
 bool Simulator::is_busy() const {
-  return vortex_->busy 
-      || snp_req_active_ 
-      || csr_req_active_;
+  return vortex_->busy;
+}
+
+bool Simulator::snp_req_active() const {
+  return snp_req_active_;
+}
+
+bool Simulator::csr_req_active() const {
+  return csr_req_active_;
 }
 
 void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {  
@@ -290,10 +316,7 @@ void Simulator::get_csr(int core_id, int addr, unsigned *value) {
 void Simulator::run() {
 #ifndef NDEBUG
   std::cout << timestamp << ": [sim] run()" << std::endl;
-#endif 
-
-  // reset the device
-  this->reset();
+#endif
 
   // execute program
   while (vortex_->busy 

hw/simulate/simulator.h

@@ -13,6 +13,8 @@
 
 #include <ostream>
 #include <vector>
+#include <sstream> 
+#include <unordered_map>
 
 class Simulator {
 public:
@@ -25,7 +27,10 @@ public:
   void load_bin(const char* program_file);
   void load_ihex(const char* program_file);
   
-  bool is_busy() const;  
+  bool is_busy() const;
+
+  bool snp_req_active() const;  
+  bool csr_req_active() const;
 
   void reset();
   void step();
@@ -48,6 +53,8 @@ private:
     unsigned tag;
   } dram_req_t;
 
+  std::unordered_map<int, std::stringstream> print_bufs_;
+
   void eval();  
 
   void eval_dram_bus();