using mshr pending request size
This commit is contained in:
Blaise Tine
204
hw/rtl/cache/VX_miss_resrv.v
vendored
Normal file
204
hw/rtl/cache/VX_miss_resrv.v
vendored
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`include "VX_cache_config.vh"
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module VX_miss_resrv #(
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parameter CACHE_ID = 0,
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parameter BANK_ID = 0,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 1,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 1,
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// Number of Word requests per cycle
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parameter NUM_REQUESTS = 1,
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// Miss Reserv Queue Knob
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parameter MSHR_SIZE = 1,
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// core request tag size
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parameter CORE_TAG_WIDTH = 1,
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// Snooping request tag width
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parameter SNP_TAG_WIDTH = 1,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef DBG_CACHE_REQ_INFO
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`IGNORE_WARNINGS_BEGIN
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input wire[31:0] debug_pc_st0,
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input wire[`NR_BITS-1:0] debug_rd_st0,
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input wire[`NW_BITS-1:0] debug_wid_st0,
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input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st0,
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input wire[31:0] debug_pc_st3,
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input wire[`NR_BITS-1:0] debug_rd_st3,
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input wire[`NW_BITS-1:0] debug_wid_st3,
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input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st3,
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`IGNORE_WARNINGS_END
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`endif
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// enqueue
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input wire enqueue_st3,
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input wire[`LINE_ADDR_WIDTH-1:0] enqueue_addr_st3,
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input wire[`UP(`WORD_SELECT_WIDTH)-1:0] enqueue_wsel_st3,
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input wire[`WORD_WIDTH-1:0] enqueue_data_st3,
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input wire[`REQS_BITS-1:0] enqueue_tid_st3,
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input wire[`REQ_TAG_WIDTH-1:0] enqueue_tag_st3,
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input wire enqueue_rw_st3,
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input wire[WORD_SIZE-1:0] enqueue_byteen_st3,
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input wire enqueue_is_snp_st3,
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input wire enqueue_snp_inv_st3,
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input wire enqueue_mshr_st3,
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input wire enqueue_ready_st3,
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output wire enqueue_full,
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// fill
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input wire update_ready_st0,
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input wire[`LINE_ADDR_WIDTH-1:0] addr_st0,
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output wire pending_hazard_st0,
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// dequeue
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input wire schedule_st0,
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output wire dequeue_valid_st0,
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output wire[`LINE_ADDR_WIDTH-1:0] dequeue_addr_st0,
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output wire[`UP(`WORD_SELECT_WIDTH)-1:0] dequeue_wsel_st0,
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output wire[`WORD_WIDTH-1:0] dequeue_data_st0,
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output wire[`REQS_BITS-1:0] dequeue_tid_st0,
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output wire[`REQ_TAG_WIDTH-1:0] dequeue_tag_st0,
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output wire dequeue_rw_st0,
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output wire[WORD_SIZE-1:0] dequeue_byteen_st0,
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output wire dequeue_is_snp_st0,
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output wire dequeue_snp_inv_st0,
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input wire dequeue_st3
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);
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wire [`MSHR_METADATA_WIDTH-1:0] metadata_table;
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`NO_RW_RAM_CHECK reg [`LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
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reg [MSHR_SIZE-1:0] valid_table;
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reg [MSHR_SIZE-1:0] ready_table;
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reg [`LOG2UP(MSHR_SIZE)-1:0] schedule_ptr, restore_ptr;
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reg [`LOG2UP(MSHR_SIZE)-1:0] head_ptr;
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reg [`LOG2UP(MSHR_SIZE)-1:0] tail_ptr;
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reg [`LOG2UP(MSHR_SIZE+1)-1:0] size;
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assign enqueue_full = (size == $bits(size)'(MSHR_SIZE));
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wire [MSHR_SIZE-1:0] valid_address_match;
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for (genvar i = 0; i < MSHR_SIZE; i++) begin
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assign valid_address_match[i] = valid_table[i] && (addr_table[i] == addr_st0);
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end
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assign pending_hazard_st0 = (| valid_address_match);
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wire dequeue_ready = valid_table[schedule_ptr] && ready_table[schedule_ptr];
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assign dequeue_valid_st0 = dequeue_ready;
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assign dequeue_addr_st0 = addr_table[schedule_ptr];
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assign {dequeue_data_st0,
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dequeue_tid_st0,
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dequeue_tag_st0,
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dequeue_rw_st0,
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dequeue_byteen_st0,
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dequeue_wsel_st0,
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dequeue_is_snp_st0,
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dequeue_snp_inv_st0} = metadata_table;
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wire mshr_push = enqueue_st3 && !enqueue_mshr_st3;
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wire [`LOG2UP(MSHR_SIZE)-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
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always @(posedge clk) begin
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if (reset) begin
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valid_table <= 0;
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ready_table <= 0;
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schedule_ptr <= 0;
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restore_ptr <= 0;
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head_ptr <= 0;
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tail_ptr <= 0;
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size <= 0;
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end else begin
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if (update_ready_st0) begin
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ready_table <= ready_table | valid_address_match;
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end
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if (enqueue_st3) begin
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assert(!enqueue_full);
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if (enqueue_mshr_st3) begin
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// returning missed msrq entry, restore schedule
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valid_table[restore_ptr] <= 1;
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ready_table[restore_ptr] <= enqueue_ready_st3;
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restore_ptr <= restore_ptr + $bits(restore_ptr)'(1);
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schedule_ptr <= head_ptr;
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end else begin
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valid_table[tail_ptr] <= 1;
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ready_table[tail_ptr] <= enqueue_ready_st3;
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tail_ptr <= tail_ptr + $bits(tail_ptr)'(1);
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size <= size + $bits(size)'(1);
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end
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end else if (dequeue_st3) begin
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head_ptr <= head_ptr_n;
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restore_ptr <= head_ptr_n;
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valid_table[head_ptr] <= 0;
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size <= size - $bits(size)'(1);
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end
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if (schedule_st0) begin
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assert(dequeue_valid_st0);
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valid_table[schedule_ptr] <= 0;
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schedule_ptr <= schedule_ptr + $bits(schedule_ptr)'(1);
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end
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end
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end
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always @(posedge clk) begin
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if (enqueue_st3 && !enqueue_mshr_st3) begin
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addr_table[tail_ptr] <= enqueue_addr_st3;
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end
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end
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VX_dp_ram #(
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.DATAW(`MSHR_METADATA_WIDTH),
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.SIZE(MSHR_SIZE),
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.BYTEENW(1),
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.BUFFERED(0),
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.RWCHECK(1)
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) metadata (
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.clk(clk),
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.waddr(tail_ptr),
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.raddr(schedule_ptr),
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.wren(mshr_push),
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.byteen(1'b1),
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.rden(1'b1),
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.din({enqueue_data_st3, enqueue_tid_st3, enqueue_tag_st3, enqueue_rw_st3, enqueue_byteen_st3, enqueue_wsel_st3, enqueue_is_snp_st3, enqueue_snp_inv_st3}),
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.dout(metadata_table)
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);
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`ifdef DBG_PRINT_CACHE_MSHR
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always @(posedge clk) begin
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if (update_ready_st0 || schedule_st0 || enqueue_st3 || dequeue_st3) begin
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if (schedule_st0)
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$display("%t: cache%0d:%0d msrq-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(dequeue_addr_st0, BANK_ID), debug_wid_st0, debug_pc_st0);
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if (enqueue_st3) begin
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if (enqueue_mshr_st3)
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$display("%t: cache%0d:%0d msrq-restore: addr%0d=%0h, ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr_st3, BANK_ID), enqueue_ready_st3);
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else
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$display("%t: cache%0d:%0d msrq-enq: addr%0d=%0h, ready=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr_st3, BANK_ID), enqueue_ready_st3, debug_wid_st3, debug_pc_st3);
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end
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if (dequeue_st3)
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$display("%t: cache%0d:%0d msrq-deq addr%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, debug_wid_st3, debug_pc_st3);
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$write("%t: cache%0d:%0d msrq-table", $time, CACHE_ID, BANK_ID);
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for (integer j = 0; j < MSHR_SIZE; j++) begin
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if (valid_table[j]) begin
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$write(" ");
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if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
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if (~ready_table[j]) $write("!");
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$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
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end
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end
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$write("\n");
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end
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end
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`endif
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endmodule
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