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Icache working

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This commit is contained in:
felsabbagh3
2020-03-08 13:59:35 -07:00
parent 3b11e1d72f
commit f315a8a44d
6 changed files with 279 additions and 200 deletions
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151
rtl/VX_dmem_controller.v
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@@ -3,18 +3,22 @@
module VX_dmem_controller (
input wire clk,
input wire reset,
// Dcache
// Dram <-> Dcache
VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req,
VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res,
// Dram <-> Icache
VX_gpu_dcache_dram_req_inter VX_gpu_icache_dram_req,
VX_gpu_dcache_dram_res_inter VX_gpu_icache_dram_res,
// Core <-> Dcache
VX_gpu_dcache_res_inter VX_dcache_rsp,
VX_gpu_dcache_req_inter VX_dcache_req,
VX_dram_req_rsp_inter VX_dram_req_rsp_icache,
// MEM-Processor
VX_icache_request_inter VX_icache_req,
VX_icache_response_inter VX_icache_rsp
// Core <-> Icache
VX_gpu_dcache_res_inter VX_icache_rsp,
VX_gpu_dcache_req_inter VX_icache_req
);
wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF;
@@ -30,17 +34,6 @@ module VX_dmem_controller (
wire[`NT_M1:0] cache_driver_out_valid; // Not used for now
wire sm_delay;
// I_Cache Signals
wire[31:0] icache_instruction_out;
wire icache_delay;
wire icache_driver_in_valid = VX_icache_req.out_cache_driver_in_valid;
wire[31:0] icache_driver_in_address = VX_icache_req.pc_address;
wire[2:0] icache_driver_in_mem_read = !(|icache_driver_in_valid) ? `NO_MEM_READ : VX_icache_req.out_cache_driver_in_mem_read;
wire[2:0] icache_driver_in_mem_write = !(|icache_driver_in_valid) ? `NO_MEM_WRITE : VX_icache_req.out_cache_driver_in_mem_write;
wire[31:0] icache_driver_in_data = VX_icache_req.out_cache_driver_in_data;
wire read_or_write_ic = (VX_icache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (|icache_driver_in_valid);
VX_shared_memory #(
.SM_SIZE (`SHARED_MEMORY_SIZE),
@@ -159,56 +152,86 @@ module VX_dmem_controller (
);
VX_d_cache #(
.CACHE_SIZE (`ICACHE_SIZE),
.CACHE_WAYS (`ICACHE_WAYS),
.CACHE_BLOCK (`ICACHE_BLOCK),
.CACHE_BANKS (`ICACHE_BANKS),
.LOG_NUM_BANKS (`ICACHE_LOG_NUM_BANKS),
.NUM_REQ (`ICACHE_NUM_REQ),
.LOG_NUM_REQ (`ICACHE_LOG_NUM_REQ),
.NUM_IND (`ICACHE_NUM_IND),
.CACHE_WAY_INDEX (`ICACHE_WAY_INDEX),
.NUM_WORDS_PER_BLOCK (`ICACHE_NUM_WORDS_PER_BLOCK),
.OFFSET_SIZE_START (`ICACHE_OFFSET_ST),
.OFFSET_SIZE_END (`ICACHE_OFFSET_ED),
.TAG_SIZE_START (`ICACHE_TAG_SIZE_START),
.TAG_SIZE_END (`ICACHE_TAG_SIZE_END),
.IND_SIZE_START (`ICACHE_IND_SIZE_START),
.IND_SIZE_END (`ICACHE_IND_SIZE_END),
.ADDR_TAG_START (`ICACHE_ADDR_TAG_START),
.ADDR_TAG_END (`ICACHE_ADDR_TAG_END),
.ADDR_OFFSET_START (`ICACHE_ADDR_OFFSET_ST),
.ADDR_OFFSET_END (`ICACHE_ADDR_OFFSET_ED),
.ADDR_IND_START (`ICACHE_IND_ST),
.ADDR_IND_END (`ICACHE_IND_ED),
.MEM_ADDR_REQ_MASK (`ICACHE_MEM_REQ_ADDR_MASK)
) icache
VX_cache #(
.CACHE_SIZE_BYTES (`ICACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`IBANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (`INUMBER_BANKS),
.WORD_SIZE_BYTES (`IWORD_SIZE_BYTES),
.NUMBER_REQUESTS (`INUMBER_REQUESTS),
.STAGE_1_CYCLES (`ISTAGE_1_CYCLES),
.REQQ_SIZE (`IREQQ_SIZE),
.MRVQ_SIZE (`IMRVQ_SIZE),
.DFPQ_SIZE (`IDFPQ_SIZE),
.SNRQ_SIZE (`ISNRQ_SIZE),
.CWBQ_SIZE (`ICWBQ_SIZE),
.DWBQ_SIZE (`IDWBQ_SIZE),
.DFQQ_SIZE (`IDFQQ_SIZE),
.LLVQ_SIZE (`ILLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`ISIMULATED_DRAM_LATENCY_CYCLES)
)
gpu_icache
(
.clk (clk),
.rst (reset),
.i_p_valid (icache_driver_in_valid),
.i_p_addr (icache_driver_in_address),
.i_p_writedata (icache_driver_in_data),
.i_p_read_or_write (read_or_write_ic),
.i_p_mem_read (icache_driver_in_mem_read),
.i_p_mem_write (icache_driver_in_mem_write),
.o_p_readdata (icache_instruction_out),
.o_p_delay (icache_delay),
.o_m_evict_addr (VX_dram_req_rsp_icache.o_m_evict_addr),
.o_m_read_addr (VX_dram_req_rsp_icache.o_m_read_addr),
.o_m_valid (VX_dram_req_rsp_icache.o_m_valid),
.o_m_writedata (VX_dram_req_rsp_icache.o_m_writedata),
.o_m_read_or_write (VX_dram_req_rsp_icache.o_m_read_or_write),
.i_m_readdata (VX_dram_req_rsp_icache.i_m_readdata),
.i_m_ready (VX_dram_req_rsp_icache.i_m_ready)
);
.clk (clk),
.reset (reset),
// assign VX_dcache_rsp.in_cache_driver_out_data = (to_shm && 0) ? sm_driver_out_data : cache_driver_out_data;
// assign VX_dcache_rsp.delay = (sm_delay && 0) || cache_delay;
// Core req
.core_req_valid (VX_icache_req.core_req_valid),
.core_req_addr (VX_icache_req.core_req_addr),
.core_req_writedata(VX_icache_req.core_req_writedata),
.core_req_mem_read (VX_icache_req.core_req_mem_read),
.core_req_mem_write(VX_icache_req.core_req_mem_write),
.core_req_rd (VX_icache_req.core_req_rd),
.core_req_wb (VX_icache_req.core_req_wb),
.core_req_warp_num (VX_icache_req.core_req_warp_num),
.core_req_pc (VX_icache_req.core_req_pc),
// Delay Core Req
.delay_req (VX_icache_rsp.delay_req),
// Core Cache Can't WB
.core_no_wb_slot (VX_icache_req.core_no_wb_slot),
// Cache CWB
.core_wb_valid (VX_icache_rsp.core_wb_valid),
.core_wb_req_rd (VX_icache_rsp.core_wb_req_rd),
.core_wb_req_wb (VX_icache_rsp.core_wb_req_wb),
.core_wb_warp_num (VX_icache_rsp.core_wb_warp_num),
.core_wb_readdata (VX_icache_rsp.core_wb_readdata),
.core_wb_pc (VX_icache_rsp.core_wb_pc),
// DRAM response
.dram_fill_rsp (VX_gpu_icache_dram_res.dram_fill_rsp),
.dram_fill_rsp_addr(VX_gpu_icache_dram_res.dram_fill_rsp_addr),
.dram_fill_rsp_data(VX_gpu_icache_dram_res.dram_fill_rsp_data),
// DRAM accept response
.dram_fill_accept (VX_gpu_icache_dram_req.dram_fill_accept),
// DRAM Req
.dram_req (VX_gpu_icache_dram_req.dram_req),
.dram_req_write (VX_gpu_icache_dram_req.dram_req_write),
.dram_req_read (VX_gpu_icache_dram_req.dram_req_read),
.dram_req_addr (VX_gpu_icache_dram_req.dram_req_addr),
.dram_req_size (VX_gpu_icache_dram_req.dram_req_size),
.dram_req_data (VX_gpu_icache_dram_req.dram_req_data),
// Snoop Response
.dram_req_because_of_wb(VX_gpu_icache_dram_req.dram_because_of_snp),
.dram_snp_full (VX_gpu_icache_dram_req.dram_snp_full),
// Snoop Request
.snp_req (0),
.snp_req_addr (0),
// LLVQ stuff
.llvq_pop (Dllvq_pop),
.llvq_valid (Dllvq_valid),
.llvq_res_addr (Dllvq_res_addr),
.llvq_res_data (Dllvq_res_data)
);
assign VX_icache_rsp.instruction = icache_instruction_out;
assign VX_icache_rsp.delay = icache_delay;
endmodule