wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

quartus build fixes

Browse Source
This commit is contained in:
Blaise Tine
2020-08-23 22:04:46 -07:00
parent 1c9445745f
commit f292e5003d
27 changed files with 241 additions and 206 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
hw/rtl/libs/VX_generic_queue.v
View File

@@ -3,7 +3,9 @@
module VX_generic_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter BUFFERED = 1
parameter BUFFERED = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1)
) (
input wire clk,
input wire reset,
@@ -13,13 +15,13 @@ module VX_generic_queue #(
output wire [DATAW-1:0] data_out,
output wire empty,
output wire full,
output wire [`LOG2UP(SIZE+1)-1:0] size
output wire [SIZEW-1:0] size
);
`STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!")
reg [`LOG2UP(SIZE+1)-1:0] size_r;
wire reading;
wire writing;
reg [SIZEW-1:0] size_r;
wire reading;
wire writing;
assign reading = pop && !empty;
assign writing = push && !full;
@@ -55,11 +57,11 @@ module VX_generic_queue #(
if (0 == BUFFERED) begin
reg [`LOG2UP(SIZE):0] rd_ptr_r;
reg [`LOG2UP(SIZE):0] wr_ptr_r;
reg [ADDRW:0] rd_ptr_r;
reg [ADDRW:0] wr_ptr_r;
wire [`LOG2UP(SIZE)-1:0] rd_ptr_a = rd_ptr_r[`LOG2UP(SIZE)-1:0];
wire [`LOG2UP(SIZE)-1:0] wr_ptr_a = wr_ptr_r[`LOG2UP(SIZE)-1:0];
wire [ADDRW-1:0] rd_ptr_a = rd_ptr_r[ADDRW-1:0];
wire [ADDRW-1:0] wr_ptr_a = wr_ptr_r[ADDRW-1:0];
always @(posedge clk) begin
if (reset) begin
@@ -86,19 +88,19 @@ module VX_generic_queue #(
assign data_out = data[rd_ptr_a];
assign empty = (wr_ptr_r == rd_ptr_r);
assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[`LOG2UP(SIZE)] != rd_ptr_r[`LOG2UP(SIZE)]);
assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[ADDRW] != rd_ptr_r[ADDRW]);
assign size = size_r;
end else begin
reg [DATAW-1:0] head_r;
reg [DATAW-1:0] curr_r;
reg [`LOG2UP(SIZE)-1:0] wr_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_next_r;
reg empty_r;
reg full_r;
reg bypass_r;
reg [DATAW-1:0] head_r;
reg [DATAW-1:0] curr_r;
reg [ADDRW-1:0] wr_ptr_r;
reg [ADDRW-1:0] rd_ptr_r;
reg [ADDRW-1:0] rd_ptr_next_r;
reg empty_r;
reg full_r;
reg bypass_r;
always @(posedge clk) begin
if (reset) begin