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quartus build fixes

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This commit is contained in:
Blaise Tine
2020-08-23 22:04:46 -07:00
parent 1c9445745f
commit f292e5003d
27 changed files with 241 additions and 206 deletions
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2
hw/rtl/libs/VX_cam_buffer.v
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@@ -13,7 +13,7 @@ module VX_cam_buffer #(
input wire [DATAW-1:0] write_data,
input wire acquire_slot,
input wire [RPORTS-1:0][ADDRW-1:0] read_addr,
output reg [RPORTS-1:0][DATAW-1:0] read_data,
output wire [RPORTS-1:0][DATAW-1:0] read_data,
input wire [CPORTS-1:0][ADDRW-1:0] release_addr,
input wire [CPORTS-1:0] release_slot,
output wire full

15
hw/rtl/libs/VX_countones.v
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@@ -2,18 +2,23 @@
`include "VX_platform.vh"
module VX_countones #(
parameter N = 10
parameter N = 10,
parameter N_BITS = $clog2(N+1)
) (
input wire [N-1:0] valids,
output reg [$clog2(N):0] count
input wire [N-1:0] valids,
output wire [N_BITS-1:0] count
);
reg [N_BITS-1:0] count_r;
always @(*) begin
count = 0;
count_r = 0;
for (integer i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
count = count + 1;
count_r = count_r + N_BITS'(1);
end
end
end
assign count = count_r;
endmodule

38
hw/rtl/libs/VX_generic_queue.v
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@@ -3,7 +3,9 @@
module VX_generic_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter BUFFERED = 1
parameter BUFFERED = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1)
) (
input wire clk,
input wire reset,
@@ -13,13 +15,13 @@ module VX_generic_queue #(
output wire [DATAW-1:0] data_out,
output wire empty,
output wire full,
output wire [`LOG2UP(SIZE+1)-1:0] size
output wire [SIZEW-1:0] size
);
`STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!")
reg [`LOG2UP(SIZE+1)-1:0] size_r;
wire reading;
wire writing;
reg [SIZEW-1:0] size_r;
wire reading;
wire writing;
assign reading = pop && !empty;
assign writing = push && !full;
@@ -55,11 +57,11 @@ module VX_generic_queue #(
if (0 == BUFFERED) begin
reg [`LOG2UP(SIZE):0] rd_ptr_r;
reg [`LOG2UP(SIZE):0] wr_ptr_r;
reg [ADDRW:0] rd_ptr_r;
reg [ADDRW:0] wr_ptr_r;
wire [`LOG2UP(SIZE)-1:0] rd_ptr_a = rd_ptr_r[`LOG2UP(SIZE)-1:0];
wire [`LOG2UP(SIZE)-1:0] wr_ptr_a = wr_ptr_r[`LOG2UP(SIZE)-1:0];
wire [ADDRW-1:0] rd_ptr_a = rd_ptr_r[ADDRW-1:0];
wire [ADDRW-1:0] wr_ptr_a = wr_ptr_r[ADDRW-1:0];
always @(posedge clk) begin
if (reset) begin
@@ -86,19 +88,19 @@ module VX_generic_queue #(
assign data_out = data[rd_ptr_a];
assign empty = (wr_ptr_r == rd_ptr_r);
assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[`LOG2UP(SIZE)] != rd_ptr_r[`LOG2UP(SIZE)]);
assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[ADDRW] != rd_ptr_r[ADDRW]);
assign size = size_r;
end else begin
reg [DATAW-1:0] head_r;
reg [DATAW-1:0] curr_r;
reg [`LOG2UP(SIZE)-1:0] wr_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_next_r;
reg empty_r;
reg full_r;
reg bypass_r;
reg [DATAW-1:0] head_r;
reg [DATAW-1:0] curr_r;
reg [ADDRW-1:0] wr_ptr_r;
reg [ADDRW-1:0] rd_ptr_r;
reg [ADDRW-1:0] rd_ptr_next_r;
reg empty_r;
reg full_r;
reg bypass_r;
always @(posedge clk) begin
if (reset) begin

22
hw/rtl/libs/VX_onehot_encooder.v
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@@ -4,19 +4,25 @@ module VX_onehot_encoder #(
parameter N = 6
) (
input wire [N-1:0] onehot,
output reg [`LOG2UP(N)-1:0] binary,
output reg valid
output wire [`LOG2UP(N)-1:0] binary,
output wire valid
);
always @(*) begin
valid = 1'b0;
binary = `LOG2UP(N)'(0);
reg [`LOG2UP(N)-1:0] binary_r;
reg valid_r;
always @(*) begin
binary_r = `LOG2UP(N)'(0);
valid_r = 1'b0;
for (integer i = 0; i < N; i++) begin
if (onehot[i]) begin
valid = 1'b1;
binary = `LOG2UP(N)'(i);
if (onehot[i]) begin
binary_r = `LOG2UP(N)'(i);
valid_r = 1'b1;
end
end
end
assign binary = binary_r;
assign valid = valid_r;
endmodule

23
hw/rtl/libs/VX_priority_encoder.v
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@@ -3,19 +3,26 @@
module VX_priority_encoder #(
parameter N = 1
) (
input wire [N-1:0] data_in,
output reg [`LOG2UP(N)-1:0] data_out,
output reg valid_out
input wire [N-1:0] data_in,
output wire [`LOG2UP(N)-1:0] data_out,
output wire valid_out
);
reg [`LOG2UP(N)-1:0] data_out_r;
reg valid_out_r;
always @(*) begin
data_out = 0;
valid_out = 0;
for (integer i = N-1; i >= 0; i = i - 1) begin
data_out_r = 0;
valid_out_r = 0;
for (integer i = 0; i < N; i++) begin
if (data_in[i]) begin
data_out = `LOG2UP(N)'(i);
valid_out = 1;
data_out_r = `LOG2UP(N)'(i);
valid_out_r = 1;
break;
end
end
end
assign data_out = data_out_r;
assign valid_out = valid_out_r;
endmodule

15
hw/rtl/libs/VX_scope.v
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@@ -14,7 +14,7 @@ module VX_scope #(
input wire changed,
input wire [DATAW-1:0] data_in,
input wire [BUSW-1:0] bus_in,
output reg [BUSW-1:0] bus_out,
output wire [BUSW-1:0] bus_out,
input wire bus_write,
input wire bus_read
);
@@ -39,6 +39,7 @@ module VX_scope #(
reg [DELTAW-1:0] delta_store [SIZE-1:0];
reg [UPDW-1:0] prev_trigger_id;
reg [DELTAW-1:0] delta;
reg [BUSW-1:0] bus_out_r;
reg [`CLOG2(SIZE)-1:0] raddr, waddr, waddr_end;
@@ -168,14 +169,16 @@ module VX_scope #(
always @(*) begin
case (out_cmd)
GET_VALID : bus_out = BUSW'(data_valid);
GET_WIDTH : bus_out = BUSW'(DATAW);
GET_COUNT : bus_out = BUSW'(waddr) + BUSW'(1);
GET_DATA : bus_out = read_delta ? BUSW'(delta_store[raddr]) : BUSW'(data_store[raddr] >> read_offset);
default : bus_out = 0;
GET_VALID : bus_out_r = BUSW'(data_valid);
GET_WIDTH : bus_out_r = BUSW'(DATAW);
GET_COUNT : bus_out_r = BUSW'(waddr) + BUSW'(1);
GET_DATA : bus_out_r = read_delta ? BUSW'(delta_store[raddr]) : BUSW'(data_store[raddr] >> read_offset);
default : bus_out_r = 0;
endcase
end
assign bus_out = bus_out_r;
`ifdef DBG_PRINT_SCOPE
always @(posedge clk) begin
if (bus_read) begin

22
hw/rtl/libs/VX_skid_buffer.v
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@@ -6,21 +6,21 @@ module VX_skid_buffer #(
input wire clk,
input wire reset,
input wire valid_in,
output reg ready_in,
output wire ready_in,
input wire [DATAW-1:0] data_in,
output reg [DATAW-1:0] data_out,
output wire [DATAW-1:0] data_out,
input wire ready_out,
output reg valid_out
output wire valid_out
);
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
always @(posedge clk) begin
if (reset) begin
use_buffer <= 0;
valid_out <= 0;
data_out <= 0;
buffer <= 0;
use_buffer <= 0;
valid_out_r <= 0;
end else begin
if (valid_in && ready_in && valid_out && !ready_out) begin
assert(!use_buffer);
@@ -33,12 +33,14 @@ module VX_skid_buffer #(
buffer <= data_in;
end
if (!valid_out || ready_out) begin
valid_out <= valid_in || use_buffer;
data_out <= use_buffer ? buffer : data_in;
valid_out_r <= valid_in || use_buffer;
data_out_r <= use_buffer ? buffer : data_in;
end
end
end
assign ready_in = !use_buffer;
assign ready_in = !use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
endmodule