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Generate define overrides based on env vars for C and Verilog.

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gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
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wgulian3
2020-03-26 04:05:23 -04:00
parent 123fb17723
commit f126a23114
7 changed files with 408 additions and 31 deletions
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3
.gitignore vendored
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@@ -4,5 +4,6 @@
./rtl/modelsim/*.vcd
*.vcd
.*
!.gitignore
*.pyc
__pycache__
__pycache__