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Added Proper Handshaking to Everything and Fixed a Couple of Bugs

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This commit is contained in:
felsabbagh3
2020-03-29 02:11:14 -07:00
parent d31b607e01
commit efac643c66
9 changed files with 523 additions and 627 deletions
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16
rtl/VX_cache/VX_bank.v
View File

@@ -331,14 +331,14 @@ module VX_bank
mrvq_hazard_st0 = 0;
reqq_hazard_st0 = 0;
snrq_hazard_st0 = 0;
for (st1_cycle = 0; st1_cycle < STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin
if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin
if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) dfpq_hazard_st0 = 1;
if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) mrvq_hazard_st0 = 1;
if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) reqq_hazard_st0 = 1;
if (snrq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) snrq_hazard_st0 = 1;
end
end
// for (st1_cycle = 0; st1_cycle < STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin
// if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin
// if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) dfpq_hazard_st0 = 1;
// if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) mrvq_hazard_st0 = 1;
// if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) reqq_hazard_st0 = 1;
// if (snrq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) snrq_hazard_st0 = 1;
// end
// end
end
wire qual_is_fill_st0;

5
rtl/VX_cache/VX_cache.v
View File

@@ -91,6 +91,8 @@ module VX_cache
output wire [31:0] dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire dram_req_because_of_wb,
input wire dram_req_delay,
output wire dram_snp_full,
@@ -183,7 +185,8 @@ module VX_cache
.dram_req_addr (dram_req_addr),
.dram_req_size (dram_req_size),
.dram_req_data (dram_req_data),
.dram_req_because_of_wb (dram_req_because_of_wb)
.dram_req_because_of_wb (dram_req_because_of_wb),
.dram_req_delay (dram_req_delay)
);

8
rtl/VX_cache/VX_cache_dram_req_arb.v
View File

@@ -68,7 +68,9 @@ module VX_cache_dram_req_arb
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire dram_req_because_of_wb
output wire dram_req_because_of_wb,
input wire dram_req_delay
);
@@ -76,7 +78,7 @@ module VX_cache_dram_req_arb
wire[31:0] dfqq_req_addr;
wire dfqq_empty;
wire dwb_valid;
wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop
wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_delay; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req);
VX_cache_dfq_queue VX_cache_dfq_queue(
@@ -101,7 +103,7 @@ module VX_cache_dram_req_arb
);
assign per_bank_dram_wb_queue_pop = per_bank_dram_wb_req & ((1 << dwb_bank));
assign per_bank_dram_wb_queue_pop = dram_req_delay ? 0 : per_bank_dram_wb_req & ((1 << dwb_bank));
assign dram_req = dwb_valid || dfqq_req;