minor updates
This commit is contained in:
14
hw/rtl/cache/VX_bank.v
vendored
14
hw/rtl/cache/VX_bank.v
vendored
@@ -459,7 +459,7 @@ module VX_bank #(
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VX_fifo_queue #(
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.DATAW (`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH),
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.SIZE (CRSQ_SIZE),
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.BUFFERED (1),
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.BUFFERED (NUM_BANKS == 1),
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.FASTRAM (1)
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) core_rsp_queue (
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.clk (clk),
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@@ -470,6 +470,8 @@ module VX_bank #(
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.data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}),
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.empty (crsq_empty),
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.full (crsq_full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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);
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@@ -508,10 +510,11 @@ module VX_bank #(
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assign dreq_byteen = writeback ? dreq_byteen_unqual : {CACHE_LINE_SIZE{1'b1}};
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VX_fifo_queue_xt #(
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VX_fifo_queue #(
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.DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH),
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.SIZE (DREQ_SIZE),
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.ALM_FULL (DREQ_SIZE-1),
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.BUFFERED (NUM_BANKS == 1),
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.FASTRAM (1)
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) dram_req_queue (
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.clk (clk),
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@@ -521,10 +524,9 @@ module VX_bank #(
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.data_in ({writeback, dreq_byteen, dreq_addr, dreq_data}),
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.data_out({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}),
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.empty (dreq_empty),
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.almost_full (dreq_almost_full),
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`UNUSED_PIN (full),
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`UNUSED_PIN (data_out_next),
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`UNUSED_PIN (empty_next),
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.alm_full(dreq_almost_full),
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`UNUSED_PIN (full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (size)
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);
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6
hw/rtl/cache/VX_fifo_queue_xt.v
vendored
6
hw/rtl/cache/VX_fifo_queue_xt.v
vendored
@@ -30,10 +30,10 @@ module VX_fifo_queue_xt #(
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reg [ADDRW-1:0] used_r;
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always @(posedge clk) begin
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if (reset) begin
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used_r <= 0;
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if (reset) begin
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full_r <= 0;
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almost_full_r <= 0;
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almost_full_r <= 0;
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used_r <= 0;
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end else begin
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assert(!push || !full);
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assert(!pop || !empty_r);
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6
hw/rtl/cache/VX_shared_mem.v
vendored
6
hw/rtl/cache/VX_shared_mem.v
vendored
@@ -157,6 +157,8 @@ module VX_shared_mem #(
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per_bank_core_req_tag}),
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.empty (creq_empty),
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.full (creq_full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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);
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@@ -225,7 +227,9 @@ module VX_shared_mem #(
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.data_in ({core_rsp_valid_unqual, core_rsp_data_unqual, core_rsp_tag_unqual}),
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.data_out({core_rsp_valid_tmask, core_rsp_data, core_rsp_tag}),
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.empty (crsq_empty),
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.full (crsq_full),
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.full (crsq_full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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);
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