minor update

2023-11-27 02:04:53 -08:00
parent 2f1171ca76
commit ebec982434
9 changed files with 15 additions and 15 deletions
--- a/hw/rtl/libs/VX_axi_adapter.sv
+++ b/hw/rtl/libs/VX_axi_adapter.sv
@@ -20,7 +20,7 @@ module VX_axi_adapter #(
    parameter TAG_WIDTH      = 8,
    parameter NUM_BANKS      = 1, 
    parameter AVS_ADDR_WIDTH = (ADDR_WIDTH - `CLOG2(DATA_WIDTH/8)),
-    parameter OUT_REG_RSP   = 0
+    parameter OUT_REG_RSP    = 0
 ) (
    input  wire                     clk,
    input  wire                     reset,