OUTPUT_REG refactoring

2021-07-23 06:58:37 -07:00
parent 4ffbcb336f
commit ea1e0f201e
12 changed files with 78 additions and 76 deletions
--- a/hw/rtl/libs/VX_stream_demux.v
+++ b/hw/rtl/libs/VX_stream_demux.v
@@ -39,8 +39,9 @@ module VX_stream_demux #(

        for (genvar i = 0; i < NUM_REQS; i++) begin  
            VX_skid_buffer #(
-                .DATAW    (DATAW),
-                .PASSTHRU (!BUFFERED)
+                .DATAW      (DATAW),
+                .PASSTHRU   (0 == BUFFERED),
+                .OUTPUT_REG (2 == BUFFERED)
            ) out_buffer (
                .clk       (clk),
                .reset     (reset),