OUTPUT_REG refactoring

2021-07-23 06:58:37 -07:00
parent 4ffbcb336f
commit ea1e0f201e
12 changed files with 78 additions and 76 deletions
--- a/hw/rtl/libs/VX_stream_arbiter.v
+++ b/hw/rtl/libs/VX_stream_arbiter.v
@@ -94,8 +94,9 @@ module VX_stream_arbiter #(
        );

        VX_skid_buffer #(
-            .DATAW    (DATAW),
-            .PASSTHRU (!BUFFERED)
+            .DATAW      (DATAW),
+            .PASSTHRU   (0 == BUFFERED),
+            .OUTPUT_REG (2 == BUFFERED)
        ) out_buffer (
            .clk       (clk),
            .reset     (reset),