OUTPUT_REG refactoring

2021-07-23 06:58:37 -07:00
parent 4ffbcb336f
commit ea1e0f201e
12 changed files with 78 additions and 76 deletions
--- a/hw/rtl/libs/VX_skid_buffer.v
+++ b/hw/rtl/libs/VX_skid_buffer.v
@@ -4,7 +4,7 @@ module VX_skid_buffer #(
    parameter DATAW          = 1,
    parameter PASSTHRU       = 0,
    parameter NOBACKPRESSURE = 0,
-    parameter USE_FASTREG    = 0
+    parameter OUTPUT_REG     = 0
 ) ( 
    input  wire             clk,
    input  wire             reset,
@@ -50,7 +50,7 @@ module VX_skid_buffer #(
    
    end else begin

-        if (USE_FASTREG) begin
+        if (OUTPUT_REG) begin

            reg [DATAW-1:0] data_out_r;
            reg [DATAW-1:0] buffer;