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OUTPUT_REG refactoring

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Blaise Tine
2021-07-23 06:58:37 -07:00
parent 4ffbcb336f
commit ea1e0f201e
12 changed files with 78 additions and 76 deletions
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20
hw/rtl/libs/VX_elastic_buffer.v
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@@ -1,10 +1,10 @@
`include "VX_platform.vh"
module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter BUFFERED = 0,
parameter FASTRAM = 0
parameter DATAW = 1,
parameter SIZE = 2,
parameter OUTPUT_REG = 0,
parameter FASTRAM = 0
) (
input wire clk,
input wire reset,
@@ -31,8 +31,8 @@ module VX_elastic_buffer #(
end else if (SIZE == 2) begin
VX_skid_buffer #(
.DATAW (DATAW),
.USE_FASTREG (BUFFERED)
.DATAW (DATAW),
.OUTPUT_REG (OUTPUT_REG)
) queue (
.clk (clk),
.reset (reset),
@@ -52,10 +52,10 @@ module VX_elastic_buffer #(
wire pop = valid_out && ready_out;
VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED),
.FASTRAM (FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (OUTPUT_REG),
.FASTRAM (FASTRAM)
) queue (
.clk (clk),
.reset (reset),