OUTPUT_REG refactoring

2021-07-23 06:58:37 -07:00
parent 4ffbcb336f
commit ea1e0f201e
12 changed files with 78 additions and 76 deletions
--- a/hw/rtl/cache/VX_cache.v
+++ b/hw/rtl/cache/VX_cache.v
@@ -250,9 +250,9 @@ module VX_cache #(
    assign mem_rsp_tag_nc_a = mem_rsp_tag_nc[NC_ENABLE +: `MEM_ADDR_WIDTH];
    
    VX_elastic_buffer #(
-        .DATAW    (`MEM_ADDR_WIDTH + `CACHE_LINE_WIDTH), 
-        .SIZE     (MRSQ_SIZE),
-        .BUFFERED (MRSQ_SIZE > 2)
+        .DATAW      (`MEM_ADDR_WIDTH + `CACHE_LINE_WIDTH), 
+        .SIZE       (MRSQ_SIZE),
+        .OUTPUT_REG (MRSQ_SIZE > 2)
    ) mem_rsp_queue (
        .clk        (clk),
        .reset      (reset),