OUTPUT_REG refactoring
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@@ -44,7 +44,7 @@ module VX_avs_wrapper #(
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);
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localparam BANK_ADDRW = `LOG2UP(NUM_BANKS);
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localparam BUFFERED_OUTPUT = (NUM_BANKS > 2);
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localparam OUTPUT_REG = (NUM_BANKS > 2);
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// Requests handling
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@@ -80,9 +80,9 @@ module VX_avs_wrapper #(
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`UNUSED_VAR (req_queue_size)
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VX_fifo_queue #(
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.DATAW (REQ_TAG_WIDTH),
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.SIZE (RD_QUEUE_SIZE),
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.BUFFERED (!BUFFERED_OUTPUT)
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.DATAW (REQ_TAG_WIDTH),
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.SIZE (RD_QUEUE_SIZE),
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.OUTPUT_REG (!OUTPUT_REG)
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) rd_req_queue (
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.clk (clk),
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.reset (reset),
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@@ -124,9 +124,9 @@ module VX_avs_wrapper #(
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for (genvar i = 0; i < NUM_BANKS; i++) begin
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VX_fifo_queue #(
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.DATAW (AVS_DATA_WIDTH),
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.SIZE (RD_QUEUE_SIZE),
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.BUFFERED (!BUFFERED_OUTPUT)
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.DATAW (AVS_DATA_WIDTH),
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.SIZE (RD_QUEUE_SIZE),
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.OUTPUT_REG (OUTPUT_REG)
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) rd_rsp_queue (
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.clk (clk),
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.reset (reset),
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@@ -151,7 +151,7 @@ module VX_avs_wrapper #(
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VX_stream_arbiter #(
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.NUM_REQS (NUM_BANKS),
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.DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH),
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.BUFFERED (BUFFERED_OUTPUT)
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.BUFFERED (OUTPUT_REG ? 1 : 0)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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@@ -739,9 +739,9 @@ always @(posedge clk) begin
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end
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VX_fifo_queue #(
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.DATAW (CCI_RD_QUEUE_DATAW),
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.SIZE (CCI_RD_QUEUE_SIZE),
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.BUFFERED (1)
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.DATAW (CCI_RD_QUEUE_DATAW),
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.SIZE (CCI_RD_QUEUE_SIZE),
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.OUTPUT_REG (1)
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) cci_rd_req_queue (
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.clk (clk),
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.reset (reset),
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